Article ID: 000083676 Content Type: Product Information & Documentation Last Reviewed: 01/28/2015

How do I use the EDERROR_INJECT JTAG instruction to simulate a CRC error in a Stratix III, Stratix IV or Arria II GX device?

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Description

To simulate a CRC error in a Stratix® III, Stratix IV or Arria® II GX device using the EDERROR_INJECT JTAG instruction, copy the code in Example 3 in AN 539: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices (PDF) into a text file and save it as a .jam file.

You can then use the command-line JAM player in the Quartus® II design software to execute the .jam file

The command would be:

quartus_jli -aerror_inject -cn <filename>.jam

where n after the -c = the cable index. To find out the cable index for the USB-Blaster™, execute:

quartus_jli -n

 

Related Products

This article applies to 5 products

Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA
Arria® II GX FPGA

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