Article ID: 000075790 Content Type: Product Information & Documentation Last Reviewed: 03/11/2014

How do I use the CHANGE_EDREG instruction to simulate a CRC error in Stratix, Stratix II, Arria GX, and Cyclone II and later series devices?



You can download the contents required to create a crc.jam file and follow the instructions below to issue the CHANGE_EDREG instruction to simulate a CRC error in Stratix®, Stratix II, Arria® GX, and Cyclone® II and later-series devices.

Using the attached JAM file, modify line #9 to an arbitrary number. This is to change the CRC checksum value.
DRSCAN 32, ;

  1. This will overwrite the CRC checksum in the Storage Register through the CHANGE_EDREG instruction.
  2. The CRC_Error pin will then go high, signaling a CRC error.

You can use the command-line JAM player in the Quartus® II design software to execute the crc.jam file

The command would be :

quartus_jli -aconfig_io -cn crc.jam

where n after the -c = the cable index. To find out the cable index for the USB-Blaster™, execute :

quartus_jli -n

Related Products

This article applies to 7 products

Cyclone® IV E FPGA
Cyclone® II FPGA
Cyclone® IV GX FPGA
Arria® GX FPGA
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Cyclone® III LS FPGA