Description
Due to limitations in the Quartus® II software versions 10.0 SP1 and earlier, you may see these spine clock errors if your project has high clock routing demands. These errors are often seen with designs utilizing multiple memory interfaces and high-speed serial interface (HSSI) channels (especially PMA Direct).
To work around these limitations, constrain your design to better utilize regional clock resources. Below are several recommendations for constraining your design.
- If your design does not use LogicLock regions, or if the LogicLock regions are not aligned to clock region boundaries, creating additional LogicLock regions and further constraining your logic may help your design to fit. Note that register packing, a synthesis optimization option, may ignore LogicLock regions. If this occurs, disable register packing for specific instances through the Quartus II Assignment Editor.
- Some periphery features may ignore LogicLock region assignments, and the global promotion process may not properly detect when this happens. Avoid such cases by assigning specific pins to the I/Os using these periphery features. Doing this ensures that the global promotion process will use the correct locations.
- Some IP MegaCore® functions apply a global signal assignment with a value of dual-regional clock by default. If you constrain the logic to a regional clock region and set the global signal assignment to regional instead of dual-regional, you can reduce the clock resource contention problems.
Improvements to clock resource optimization are scheduled in the Quartus II software version 10.1, with additional improvements scheduled for later releases.