Article ID: 000073709 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get "Following nodes use the same resource" errors related to INTERQUAD_TXRX_CLK, SPINE_CLOCK or CLOCK CONTROL BLOCK?

Environment

  • Clock
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see such errors, when the design uses both the GXB transceiver channels in the basic (PMA-direct) or deterministic mode and the LVDS channels in the soft-CDR mode.

    The errors are related to PCLK clock network resource sharing conflict between the GXB transceiver channels and the LVDS channels.

    The following workarounds may be helpful:

    1. Turn off the transceiver interface clock Global Signal assignment in the Assignment Editor. This will force transceiver clock to utilize other clock resources. Clocks with large fanout may have difficulty meeting the timing. You can try making this assignment on the clocks with smaller fanout to avoid such timing issues.

    2. Modify location placement of either the affected transceiver channels or the LVDS channels.

    If it does not resolve the issue, you could file a Service Request at http://mySupport.altera.com

    Related Products

    This article applies to 1 products

    Stratix® IV GX FPGA

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