Article ID: 000082927 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Will I get a correct datarate when using dynamic reconfiguration to configure transceiver channels to listen to ATX or CMU PLLs driving the central clock divider in Stratix IV GX and GT devices when using Quartus II Software Version 10.0?

Environment

  • Stratix® IV GT FPGA
  • Stratix® IV GX FPGA
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Description

No, you will not get a correct datarate when using dynamic reconfiguration to configure transceiver channels to listen to ATX or CMU PLLs driving the central clock divider in Stratix IV GX and GT devices when using Quartus II Software Version 10.0?

The following configurations are affected.

  • Using dynamic reconfiguration to reconfigure select an ATX PLL will result in an incorrect receiver datarate.
  • Using dynamic reconfiguration to switch from a CMU PLL to an ATX PLL will result in an incorrect datarate on the transmitter and receiver.

To work around this issue, you can download the following patches.

Quartus 9.1-SP2

This patch is incompatible with patches 2.17, 2.76 and 2.35.

Quartus 10.0

This patch is incompatible with patches 0.02 and 0.15.

This issue is currently scheduled to be fixed in a future version of the Quartus II Software.

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