Article ID: 000081966 Content Type: Troubleshooting Last Reviewed: 04/01/2013

Are the Partial Reconfiguration output pins on Stratix V, Arria V and Cyclone V devices configured as Open Drain by default, when these pins are enabled in my Quartus II project?

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BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description In Quartus® II software versions 12.1 and earlier, if the Partial Reconfiguration (PR) pins are enabled for Stratix® V, Arria® V or Cyclone® V devices, the outputs will not be configured as Open Drain, and they will be powered by the VCCIO supply of the bank that they reside in.
Resolution Open Drain functionality will be provided as an option for these pins in a future version of the Quartus II software. 

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This article applies to 15 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

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