Article ID: 000080928 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How do I implement the ALTLVDS_RX and ALTLVDS_TX megafunctions with External PLL mode in Arria II GX devices?

Environment

  • Arria® II GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Arria® II GX devices use the same connection scheme as Stratix® IV GX devices for the ALTVDS_RX and ALTLVDS_TX megafunctions when using External PLL mode.  You can refer to the LVDS Interface with the Use External PLL Option Enabled section in High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices (PDF) for instructions.

Note, the phase shift example used in this section assumes the clock and data are edge aligned at the pins of the FPGA. For other clock relationships, Altera recommends creating the ALTLVDS_TX and ALTLVDS_RX megafunction initially without using the External PLL option. Set the phase shifts you require in the respective megafunction, then note the phase shift and duty cycle settings for the three PLL output clocks in the Quartus® II software Compilation Report - Fitter - Resource Section - PLL Usage. Once you have the correct phase shift and duty cycle settings for your parameterization, you can implement External PLL mode in your design, and enter the phase shift and duty cycle values for each output clock based on the values you previously noted from the PLL Usage report.

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