Due to a problem in the Quartus® II software versions 10.0, 10.0 SP1, 10.1, and 10.1 SP1, you may see this critical warning when implementing the ALTLVDS_TX megafunction using external PLL mode. When using the external PLL mode, you need to add registers in your RTL prior to the tx_in port, and those registers must be clocked with the PLL output that is used as the slow-speed "parallel" or "coreclk" which is equal to the data rate divided by the serialization factor.
This problem occurs if you enable the Use external PLL option on the General page of the ALTLVDS_TX MegaWizard™ Plug-in Manager after you select either tx_coreclock or tx_inclock as the value for the Register 'tx_in' input port using parameter on the Frequency/PLL settings page. Due to the problem in the Quartus II software, the ALTLVDS_TX variation file may be written incorrectly so that the high speed clock from the PLL is connected to the registers. This may violate the clock network Fmax for the device.
To verify whether your design is affected by this problem, open the variation file, and search for the following parameter or generic:
- Verilog HDL (in the defparam section):
ALTLVDS_TX_component.registered_input - VHDL (in the GENERIC MAP section):
registered_input
The correct parameter should be OFF when using external PLL mode. The value may be set incorrectly to TX_CORECLOCK or TX_INCLOCK.
To fix this problem, follow these steps:
- Open the ALTLVDS_TX varation using the MegaWizard Plug-In Manager
- On the General page, disable the option Use external PLL
- On the Frequency/PLL settings page, disable the option Register 'tx_in' input port using
- Go back to the General page, and re-enable the option Use external PLL
- Click Finish so these changes are made to the variation file
This problem is fixed beginning with the Quartus II software version 11.0.