Article ID: 000080795 Content Type: Troubleshooting Last Reviewed: 10/31/2023

Why I can’t place Intel® Stratix® 10 FPGA partitions adjacent to the I/O Bank of EMIF/PHY Lite/LVDS Interfaces, export, and reuse them in another project?


  • Intel® Quartus® Prime Pro Edition

    Critical Issue


    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 18.0 or earlier, when a partition is placed in the row clock region adjacent to EMIF/PHY Lite/LVDS interfaces in one project (or in a developer project) and is reused using the QDB_FILE_PARTITION assignment into another project (or into consumer project), you will see the following internal error:

    Internal Error: Sub-system: LAB, File: /quartus/legality/lab/lab_nd_config_creator_module.cpp, Line: 1006

    • The green box in Figure defines a clock sector. 1
    • A row clock region is a half-clock sector-wide and one LAB row tall, represented by the red dotted box in Figure. 1
      • In the consumer project, f the reused partition has a placement in this region, you might see the above internal error.



    To work around this problem, use logic lock regions in the developer project to avoid placing the partition in the row clock region adjacent to the EMIF/PHY Lite/LVDS Interfaces.

    • In the developer project, use logic lock region constraints to restrict the placement of the partition to be exported to half clock sector away from the EMIF/PHY Lite/LVDS interfaces or the I/O bank (constrain outside the highlighted yellow region). Compile and export the partition at the final stage.
    • In the consumer project, the exported partition, when reused, will maintain the placement defined in the developer project.

    This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.