Article ID: 000087358 Content Type: Troubleshooting Last Reviewed: 05/04/2018

Why can't I compile Intel® Stratix® 10 partitions exported from another project with a different top level?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in Intel® Quartus® Prime Pro software version 18.0 or earlier, when two partitions are compiled in two different projects with top_level_1.sv and top_level_2.sv, and are reused using the QDB_FILE_PARTITION assignment into a third project with top_level_3.sv you will see the following Internal Error because of overlapping row clock region:

    Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/altera_arch_common/altera_arch_re_network_routing_constraints.cpp

    The three top level files, top_level_1.sv, top_level_2.sv and top_level_3.sv are from 3 different designs and each design is different in terms of periphery interfaces, design blocks used etc. So, the developer project (projects with top_level_1.sv and top_level_2.sv) where the partitions are initially compiled and exported from does not have the overall information about the consumer project (project with top_level_3.sv) where the two exported partitions are reused.

    • A clock sector defined by the green box in Figure. 1
    • A row clock region is half-clock sector wide and one LAB row tall represented by the red dotted box in Figure. 1
      • In consumer project when two reused partitions overlap in this region, you will see the above Internal Error
    Resolution

    To work around this problem use logic lock regions in the developer project to avoid having two reused partitions occupy the same row clock region in the consumer project.

    For example:

    • From the consumer project where the two partitions will be reused, determine the approximate placement of the yellow and purple partitions. Choose the logic lock constraints for the two partitions such that there is no overlap of the row clock region.
    • In the developer project, with the top_level_1.sv, use logic lock region constraints identified from the consumer project for the purple partition, followed by compilation and export of the partition at final stage.
    • In the developer project, with the top_level_2.sv, use logic lock region constraints identified from the consumer project for the yellow partition, followed by compilation and export of the partition at final stage.
    • The exported partitions when reused in the consumer project, with the top_level_3.sv, will maintain the placement defined in the developer projects using non overlapping logic lock constraints.

    This problem is scheduled to be fixed in a future version of the Intel Quartus Prime Pro software.

    Why I can’t place Intel® Stratix® 10 partitions adjacent to Transceiver Bank, export and reuse in another project?

    Why I can’t place Intel® Stratix® 10 partitions adjacent to the I/O Bank of EMIF/PHY Lite/LVDS Interfaces, export and reuse in another project?

    Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp

    Internal Error: Sub-system: LALE, File: /quartus/legality/lale/lale_new_solver.cpp

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