Article ID: 000077792 Content Type: Troubleshooting Last Reviewed: 01/15/2016

When using the Arria V GZ and Stratix V Hard IP for PCI Express in multiple packets per cycle mode, why are the signals rx_st_bardec2 and rx_st_bar2 not created?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the IP generation, these signals are not automatically exported when mutliple packets per cycle is checked.
    Resolution

    Export the signals rx_st_bardec2 in altpcie_sv_hip_ast_hwtcl.v to the top level output of rx_st_bar2 when using multiple packets per cycle, as shown below:

    output [7:0] rx_st_bar2,

    assign rx_st_bar2       =  rx_st_bardec2[7:0];

    Related Products

    This article applies to 4 products

    Stratix® V FPGAs
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA