Article ID: 000076815 Content Type: Troubleshooting Last Reviewed: 01/13/2016

Why are rx_st_sop, rx_st_eop, tx_st_sop and tx_st_eop only a single bit wide when Enable multiple packets per cycle was set when configurating the Arria 10 Avalon-ST Interface for PCIe Hard IP in Gen3 x8 mode?

Environment

  • Quartus® II Subscription Edition
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to an issue in the Quartus® II software versions 14.1.1 and earlier, the RTL wrapper file for the Gen3 x8 Arria® 10 Hard IP for PCI® Express incorrectly maps only a single bit of the lower level two bit wide rx_st_sop, rx_st_eop, tx_st_sop and tx_st_eop signals when Enable multiple packets per cycle is set.
    Resolution

    To work around this issue, modify the RTL wrapper file, <variation name>.v or <variation name>.vhd to export both bits of each signal.

    This issue is scheduled to be fixed in a future release of the Quartus II software.

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