Article ID: 000076685 Content Type: Troubleshooting Last Reviewed: 08/21/2012

Why is my PCI Express core's tx_out always HiZ during simulation?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When simulating your PCI Express® core you may observe that the PCI Express core appears to come out of reset properly and begin Link Initialization, but does not complete Link Initialization and the tx_out[n] port appears to be continuously in the HiZ state.

This may be the result of your testbench configuration, specifically the configuration of the test_in bus to speed up serial simulation.

Resolution

To workaround this issue, configure your testbench to speed up link initialization, by setting test_in[0] = 1. 

For simulation, it is recommended that you set test_in[39:0] = 0x0AD or 0x0A9. 

The meaning of these bits are as listed below:

[7] = Disable power management

[5] = Disable the core from entering Compliance Mode

[3] = FPGA mode

[2] = Disable scrambling

[0] = Speed up serial simulation

 

 

Related Products

This article applies to 4 products

Stratix® V GX FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA
Stratix® V GT FPGA

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