You can set test_in on the PCI Express® DUT model to “1” to accelerate the MegaCore® function initialization counters. Also, you must set the rp_test_in on the BFM Root Complex to “1” if using the testbench and BFM Root Complex.
The simulation can also be speeded up by modifying the following testbench VHDL generics/Verilog HDL parameters:
a) set "FAST_COUNTERS" to "1" to make the timing counters in the PCIe® core operate faster.
b) set “PIPE_MODE_SIM” to "1" to enable PIPE as opposed to serial mode simulation in the testbench.