Article ID: 000076079 Content Type: Troubleshooting Last Reviewed: 03/15/2023

Why does my ALTLVDS_TX Intel® FPGA IP with external PLL not functioning correctly in Arria® V, Cyclone® V, and Stratix® V devices when using the Quartus® II software version 14.0?

Environment

    Quartus® II Subscription Edition
    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

There is a known problem when using the PLL Reconfig Controller Intel® FPGA IP with the ALTLVDS Intel® FPGA IP in external PLL mode, in the Quartus® II software version 14.0 when using Arria® V,  Cyclone® V, and  Stratix® V devices.

After compiling and fitting the design, you might find that the duty cycle for the C1 counter reported in the Timing Analyzer does not match the calculation that is described in the related solution for a user defined data rate.

Resolution

To work around this, the PLL Reconfiguration Controller must be disconnected from the external PLL IP that is driving the ALTLVDS Intel FPGA IP.

This problem is scheduled to be fixed in a future version of the Intel® Quartus® software.

 

 

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This article applies to 15 products

Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Stratix® V GX FPGA
Arria® V GX FPGA
Cyclone® V GT FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Arria® V GZ FPGA
Cyclone® V E FPGA
Cyclone® V GX FPGA
Arria® V GT FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

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