Article ID: 000075761 Content Type: Error Messages Last Reviewed: 08/27/2013

Warning: No remapping logic cells found for PLL <PLL_Name> with non-phase dynamic reconfiguration enabled



You will get this warning message if you enable the dynamic reconfiguration ports in the ALTPLL megafunction without implementing the ALTPLL_RECONFIG megafunction.

When using the ALTPLL megafunction, the Quartus® II software will attempt to do the best routing for PLL counter outputs based on the specific design resource requirements. For example, C0 might be remapped to C3. If the ALTPLL_RECONFIG megafunction is implemented, the counter remapping will be done automatically and is transparent to the user.

If you are not using the ALTPLL_RECONFIG megafunction, use the 'Preserve PLL Counter Order'  assignment can be used to prevent the output counter(s) from remapping.

You can follow the sequnece below to optimize the PLL output counters for your design:

1. Compile the design and check the compiler report to see which counter is connected to which clock output.
2. Modify the PLL clock out connection in your RTL to match the order (as indicated in the PLL usage report).
For example: if you see clkout0 àSPAN> counter 3, then move all the output connections of clockout0 to clkout3, do this for all other clock outputs.
3. Compile the design again, this time with “Preserve PLL Counter Order” set to ON for the PLL in the Assignment Editor.

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Cyclone® IV E FPGA