The "Preserve Counter Order" logic option keeps Quartus II from being able to rotate the counter outputs to meet the possible fanout requirements of the design. For example, when "Preserve Counter Order" is not used, the clock placed on C0 in the wizard may be rotated to C2 during the fitting stage of compilation to successfully route the design.
The best work-around for this no-fit issue is to first compile the design without enabling the PLL reconfiguration feature. Then, once the optimal counter order is determined, modify the PLL to match that order (as indicated in the PLL usage report), and then enable the PLL-reconfiguration feature. Quartus II will then preserve this counter order because reconfiguration is enabled and you will have a successful fit with your design.