Article ID: 000077257 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why can't the Quartus II software place all my PLL outputs when I'm using the dynamic reconfiguration option?


  • PLL
    Description This problem may occur when using the PLL reconfiguration option in the Quartus® II software, and you will receive a no-fit error. When you generate an altpll instance without the dynamic reconfiguration option, the Quartus II fitter may rotate the PLL counters to improve routability. When PLL reconfiguration is used Quartus II does not rotate the counters and instead the PLL MegaWizard will match that order by automatically turning on the "Preserve Counter Order" logic option.

    The "Preserve Counter Order" logic option keeps Quartus II from being able to rotate the counter outputs to meet the possible fanout requirements of the design. For example, when "Preserve Counter Order" is not used, the clock placed on C0 in the wizard may be rotated to C2 during the fitting stage of compilation to successfully route the design.

    The best work-around for this no-fit issue is to first compile the design without enabling the PLL reconfiguration feature. Then, once the optimal counter order is determined, modify the PLL to match that order (as indicated in the PLL usage report), and then enable the PLL-reconfiguration feature. Quartus II will then preserve this counter order because reconfiguration is enabled and you will have a successful fit with your design.

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    This article applies to 1 products

    Stratix® II FPGAs