Intel's 2023 Outstanding Researcher Awards Recognize Fifteen Academic Researchers


  • Intel university-sponsored research is an important part of Intel's mission to create world-changing technology that improves the lives of everyone on the planet.

  • Intel's 2023 Outstanding Researcher Awards recognize fifteen leading worldwide academic researchers conducting Intel university-sponsored research.

  • These research contributions advance today's computing by building upon Intel technologies and advancing the state of the art.



Intel is pleased to present its 2023 Outstanding Researcher Awards (ORAs) to fifteen leading academic researchers. The annual award program recognizes the exceptional contributions made through Intel university-sponsored research that help further Intel’s mission of creating world-changing technology that improves the lives of everyone on the planet.

Intel's ORAs are part of Intel's Corporate Research Council, which participates in research initiatives with prominent university science and technology centers and other ecosystem participants. With projects spanning the design of materials via machine learning, scalable optimization for diverse computing platforms, domain-specific compilers and novel accelerator architectures, metrology, field-programmable gate arrays (FPGAs), novel semiconductor devices, privacy-preserving knowledge transfer, and more, these Intel-sponsored research collaborations are advancing today's computing into future technologies.

“Intel’s academic research projects are a core part of the company’s strategy to explore critical research paths,” said Dr. Aravind Dasu, co-director of Intel's Corporate Research Council.

“We are pleased to recognize the important contributions of these carefully selected researchers in our 2023 Outstanding Researcher Awards. We wish them each sincere congratulations,” said Dr. Henning Braunisch, co-director of Intel's Corporate Research Council.

The winners of Intel's 2023 Outstanding Researcher Awards are:

Left to right, first row: Alán Aspuru-Guzik, Caroline Trippel, Chris Kim, Henrik Sønsteby
Second row: Jesús del Alamo, Joerg Appenzeller, Michael Kögel, Nam Sung Kim
Third row: Reza Shokri, Sebastian Brand, Shimeng Yu, Shreyas Sundaram
Fourth row: Vaughn Betz, Yanjie Shao, Zhiru Zhang

Professor Alán Aspuru-Guzik, University of Toronto, Canada
Inverse Design of Functional Molecular Materials by Graph Reinforcement Learning

Infusing artificial intelligence (AI) into materials science has the potential to unlock automated end-to-end materials discovery through self-driving materials laboratories. In collaboration with the Matter Lab at the University of Toronto, led by Prof. Aspuru-Guzik, an AI-based framework was explored for building self-driving laboratories for real-world materials design. Examples include ChemOS 2.0, a software framework for connecting different pieces of complex chemistry to aggregate relevant experimental and simulation data for AI-guided materials design demonstrated on molecular lasers. Further research also infuses new AI methods along different parts of the automation pipeline, including the use of generative AI to identify chemical structures from incomplete information provided by real-world characterization machines and a new molecular text representation for modular molecular design.


Professor Caroline Trippel, Stanford University, USA
Automatically Extracting Formal Processor Models from Verilog RTL for Scalable Hardware Security Verification

Current formal verification tools often do not scale to enable efficient validation of large hardware designs. This project aims to abstract processor hardware models to dramatically speed up security proofs using formal methods. Prof. Trippel’s group is demonstrating that the human effort needed to abstract several open-source fifth generation reduced instruction set computer (RISC-V) processors can be substantially lowered using their tools.


Professor Chris Kim, University of Minnesota, USA
Demonstration of a Domain Specific Accelerator Chip with Coupled Oscillator Ising Solver Cores

This research has addressed a challenge in designing an oscillatory Ising machine with dense connectivity while prior works, whether in mixed-signal complementary metal-oxide-semiconductor (CMOS) technology, using photonics, or leveraging quantum properties have been limited in applicability due to local connectivity. The team has demonstrated a working processor that could be a key component in a future processor that efficiently solves combinatorial optimization problems that are commonplace in many applications.


Professor Henrik Sønsteby, University of Oslo, Norway
Templating Epitaxial Oxide Conductors by ALD for Advanced Devices

Integrating complex oxides in advanced microelectronics requires lattice-matched interfaces to achieve maximum performance in thin films. However, creating lattice-matching epitaxial complex oxide layers is challenging without advanced deposition techniques and large thermal budgets. Through thoughtful precursor and co-reactant choices, the research team led by Prof. Sønsteby has developed an epitaxial atomic layer deposition (ALD) process in which the concentration of a dopant can be used to tune the lattice parameters of the conductive complex oxide to match those of the underlying dielectric oxide.  Most importantly, the team has demonstrated the as-grown epitaxial conductive complex oxide layers at a reduced temperature using standard atomic layer deposition processing and equipment.


Professor Jesús del Alamo and Dr. Yanjie Shao, Massachusetts Institute of Technology, USA
Exploring the Limits of Vertical-Nanowire Tunnel Field-Effect Transistors in the Nanoscale

In this project, the team demonstrated vertical nanowire tunnel field-effect transistors (TFETs) with characteristics that push the current state of the art. The team showed record on-state performance among TFETs reported in the literature and improved subthreshold slope in broken-band systems. The team also demonstrated a performance boost over state-of-the-art metal-oxide-semiconductor FETs at the targeted operating voltage, which has long been pursued for TFETs.


Professor Joerg Appenzeller, Purdue University, USA
Performance Enhancers, Novel Device Structures and Fabrication Processes for Monolayer TMD p-FETs

Prof. Appenzeller’s group is working on building high-performance p-channel metal oxide semiconductor (PMOS) tungsten-di-selenide transistors, a critical piece to realize a scaled front-end complementary metal oxide semiconductor (CMOS) transition metal dichalcogenide (TMD) technology. The 2D research community has struggled to achieve high-currents in p-type transistors because of high contact resistance. The Purdue team used hybrid charge-transfer and molecular doping to fabricate a transistor with some of the highest PMOS drive currents reported to date. They are also working on implementing a doped, raised source-drain structure, which has shown promising results.


Professor Nam Sung Kim, University of Illinois Urbana-Champaign, USA
Rethinking Communication Infrastructure for Edge and Cloud Applications

Prof. Kim and his team of researchers have been conducting advanced system innovations that promote new technologies on Intel architecture platforms to enhance various data center workloads, including AI, machine learning (ML), and key-value store to optimize data center operations. In this project, his team has been instrumental in developing several cutting-edge technologies using Intel processors and field-programmable gate arrays (FPGAs) that showcased the feasibility and improvements of new processor and platform features for future data center architecture. The project had a great impact on the associated academic research directions and produced multiple top conference publications and technology available to the community.


Professor Reza Shokri, National University of Singapore, Singapore
Robust and Privacy-Preserving Knowledge Transfer for Heterogeneous Decentralized Learning

In this project, the research team led by Prof. Reza Shokri designed and implemented privacy attacks as well as a system for privacy auditing of machine learning models. Their tool “Privacy Meter” simulates a range of privacy attacks including variants of membership inference to assess the privacy risks of machine learning algorithms. This research was validated in the Intel federated machine learning framework “OpenFL”.


Dr. Sebastian Brand and Michael Kögel, Fraunhofer Institute for Microstructure of Materials and Systems, Germany
Enhancement of the Lock-In Thermography Analysis for the Improvement of the Resistive Defect Isolation in All Three Spatial Dimensions

Dr. Brand and his team have been instrumental in enhancing the detection resolution of lock-in thermography (LIT) systems at Intel by pioneering the use of thermal synthetic aperture, a first-in-the-industry use case. LIT is a critical fault isolation capability widely applied at Intel, enabling the pinpointing of internal electrical failures on complex heterogeneous package architectures in a non-destructive fashion. The team augmented their aperture extension approach with an AI-enabled methodology to further improve the depth localization capability for electrical failures. The developed methodologies have been validated at Intel using highly complex use cases and have resulted in significant resolution improvements, effectively setting a new research direction for LIT technology.


Professor Shimeng Yu, Georgia Institute of Technology, USA
Simulation of Probabilistic Learning Ecosystems

Modern computer hardware is primarily based upon determinist zeros and ones, while various phenomena in nature manifest a probabilistic behavior. This project leverages conventional and emerging technologies and novel hardware-software co-design for pathfinding of super energy-efficient probabilistic hardware for computation with robustness. The team prototyped scalable designs not only for Bayesian deep neural networks of AI, but also for non-polynomial (NP) hard combinatorial optimization.


Professor Shreyas Sundaram, Purdue University, USA
Robust and Scalable Runtime Optimization and Tuning for Diverse Computing Platforms

Prof. Sundaram and his team at Purdue University addressed the problem of in-field adaptive control of large systems that scales to tens of control parameters in uncertain environments while meeting safety properties. The team developed advanced model-based and model-free approaches with a focus on sampling efficiency to enable fast convergence to improved configurations with reduced training data. A grey-box model-based reinforcement learning approach was developed that provides a rapprochement between standard model-based optimal control and modern data-driven learning. To address the cases where the target system model is not available, the team developed novel black-box reinforcement learning-based algorithms that balance exploration and exploitation with a focus on discrete action spaces to handle practical use cases.


Professor Vaughn Betz, University of Toronto, Canada
Crossroads 3D FPGA Research Center

In this project, the research team led by Prof. Betz made many significant contributions to the area of field-programmable gate array (FPGA) technology. This includes enhancements to FPGA design mapping tools to leverage 3D programmable architectures and reconfigurable acceleration devices. In addition, the team demonstrated some of the highest-performance implementations of AI networks using FPGA acceleration. Additionally, the team made contributions to the research community by providing numerous open-source benchmarks.


Professor Zhiru Zhang, Cornell University, USA
Verifying Domain-Specific Optimization in HeteroCL using Polyhedral Analysis

The exponential growth of design and verification complexity calls for a seamless framework for hardware/software co-design with correctness assurance at higher levels of abstraction. Prof. Zhang and his team at Cornell have been conducting pioneering research and made significant contributions in this area. HeteroCL, a Python-based domain-specific language and a compilation flow for software-defined heterogeneous computing, decouples algorithm specification from hardware customizations in compute, data types, and memory architectures, which allows programmers to explore various trade-offs and generates efficient hardware implementations for given application workloads. It incorporates formal methods such as polyhedral analysis for verifying hardware customizations. HeteroCL was used to model the evolving micro-architecture design of an Intel fully homomorphic encryption accelerator, with the overall development effort reduced from months to a week. The model achieved high cycle accuracy in simulation and helped catch correctness issues at an early design stage.


Learn more about past recipients of Intel’s Outstanding Researcher Awards:
Seven Academic Researchers Receive Intel's 2022 Outstanding Researcher Awards
Intel's 2021 Outstanding Researcher Awards Recognize 17 Academic Researchers
Intel’s 2020 Outstanding Researcher Awards Recognize 18 Academic Researchers