Intel’s 2022 Outstanding Researcher Award winners from left to right, top row: Ramesh Karri and Gregory Parsons. Middle row: Giulia Pedrielli, Borivoje Nikolic, and Joan Daemen. Bottom row: Giovanni Maria Farinella and Felix Casanova.
Intel has recognized seven leading academic researchers with 2022 Outstanding Researcher Awards (ORAs). The annual award program recognizes exceptional contributions made through Intel university-sponsored research to help further Intel’s mission of creating world-changing technology to improve daily life.
The ORAs are part of Intel's Corporate Research Council, which participates in research initiatives with prominent university science and technology centers, and other ecosystem participants. With projects such as optimizing spin to charge conversion in magneto-electric spin orbit devices for building transistors, to addressing vulnerabilities in authenticated encryption, to developing digital twins for streamlining semiconductor manufacturing processes, these Intel-sponsored research collaborations are advancing today's computing into future technologies.
“Intel strongly values academic research. The company is committed to supporting innovative and explorative research into critical technology paths,” said Henning Braunisch, co-director of Intel's Corporate Research Council.
“Each year, we carefully select researchers based on aspects of the sponsored research such as technical difficulty, fundamental insights, and industry relevance particularly to Intel. We extend our well-deserved congratulations to the 2022 Outstanding Research Award winners,” said Aravind Dasu, co-director of Intel's Corporate Research Council.
The 2022 Intel Outstanding Research Award winners are:
Professor Ramesh Karri, New York University, USA
The Path Towards System-on-Chip Survivability
In this project, the research team lead by Prof. Karri demonstrated the Patching Blocks architecture, which leverages field-programmable gate arrays to address in-field device survivability by monitoring security bugs and performing corrective actions. The team also proposed a systemic approach that guides designers towards maximizing “patchability” to various intellectual property blocks (IPs) in the system, given a target resource overhead.
Professor Gregory Parsons, North Carolina State University, USA
System-Level Understanding of Area Selective ALD of Dielectrics
Low-defect to no-defect area-selective deposition (ASD) solutions are needed for tight-pitch and defect-sensitive applications. Approaches using self-assembled monolayers or small-molecule inhibitors can cause point defects or non-desirable topographies at interfaces. In his research, Prof. Parsons is developing a molecule-free deposition and etch approach for ASD of HfO2 on Si/metal vs. dielectric.
Professor Giulia Pedrielli, Arizona State University, USA
Digital Twin in Supply Chain
Prof. Pedrielli’s Digital Twin in Supply Chain research aims to develop digital twins to streamline semiconductor manufacturing processes and intends to adaptively generate models for the analysis and control of high-cost, high-impact equipment such as lithography and etch tools. Her team successfully developed the digital twin models using Python and other software and enabled pilot implementation. The software was released and tested for both photolithography and dry etch. In addition to the software tools, this work led to the submission of "DTFab: A Digital Twin Based Approach for Optimal Reticle Management Problem in Photolithography" to the special issue "Simulation and Artificial Intelligence" organized for the Springer Journal of Systems Science and Systems Engineering, and a request for an invited paper for the "Modeling and Analysis of Semiconductor Manufacturing (MASM)" technical cluster at the 2023 INFORMS Winter Simulation Conference.
Professor Borivoje Nikolic, University of California, Berkeley, USA
Projects in the Berkeley Wireless Research Center
Prof. Nikolic and the researchers from the Berkeley Wireless Research Center, as well as the ADEPT and SLICE labs, have been instrumental in promoting Intel’s process technologies such as Intel 16 and fabricating multiple chips in the technology using automated generator-based design flows based on Berkeley Analog Generator and Chipyard. Prof. Nikolic has been a key proponent of using the Intel 16 process node for an undergraduate tape-out class at the University of California, Berkeley and has worked with Intel to develop design flows and course materials around the Intel 16 technology, which is in the process of being shared at multiple universities across the United States.
Professor Joan Daemen, Radboud University, Netherlands
Authenticated Encryption of Content of Memory External to a Processor
In this project, the research team led by Prof. Daemen worked on lightweight encryption schemes including the BipBip tweakable block cipher and the Subterranean stream cipher with three cycles latency at 4.5 GHz, which sets a new direction for addressing memory-safety vulnerabilities with negligible performance overhead.
Professor Giovanni Maria Farinella, University of Catania, Italy
Scene Graphs for Long Range Video Understanding
Real-world videos are long, unstructured and difficult to index. This joint research project investigates a formalization of suitable representations for long-range first-person video understanding via learning structured representations, termed Egocentric Action Scene Graphs. The team created a new dataset for first-person action scene graphs with a significant impact to enable applications around long-range video understanding via learning action scene graphs.
Professor Felix Casanova, CIC nanoGUNE, Spain
Optimizing Spin to Charge Conversion and Integration of a Fully Functional MESO Device
The research team led by Prof. Casanova experimentally studied spin to charge conversion in a variety of materials and developed understanding of the scaling laws that guide material development efforts for the magneto-electric spin orbit (MESO) device output module. The team also demonstrated a fully integrated MESO device, where a ferromagnet was switched with the application of a voltage across a magnetoelectric stack, and its direction was read via the inverse spin Hall effect.