The 69th International Solid-State Circuits Conference (ISSCC), sponsored by IEEE and Solid-State Circuits Society (SSCS), will take place virtually, between February 20-28, 2022. The ISSCC conference is the foremost global forum for the presentation of advances in solid-state circuits and systems-on-a-chip and is geared towards integrated circuit design engineers, academicians, students, and architects.
At the conference, Intel will preview R&D in key technologies including IP building blocks that address the major challenges associated with building next-generation products and the co-optimization of integrated systems. These next-generation improvements come from advances in overall system-level co-optimization of process, packaging, memory, thermals, power delivery, and security that complement Moore’s law scaling.
In addition, Intel will provide updates on products including Ponte Vecchio, a multi-tile 3D stacked processor for Exascale computing. The GPU incorporates over 100B transistors spread across 47 functional tiles and five process nodes and enables the Aurora Supercomputer which is expected to achieve more than 2 ExaFlops of peak performance. Intel will also detail Sapphire Rapids, a new multi-die Intel® Xeon® Scalable Processor that features increased core counts and integrated accelerators supporting AI, crypto, compression, and data streaming. Highlighted as part of Intel’s contributions to the development of blockchain technologies is a mining application-specific integrated circuit (ASIC) with innovative technologies that reduce energy consumption.
During ISSCC, 163 technologists from Intel will present 16 papers including 11 from Intel authors and five collocative papers with universities, eight demos including five from Intel and three university collaborations, and four forum presentations at the conference. Intel will also participate in a panel and present one tutorial.
Papers will be available to members at the IEEE Xplore website.
Intel Papers and Demos
- Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing
W. Gomes, A. Koker, P. Stover, D. Ingerly, S. Siers, S. Venkataraman, C. Pelto, T. Shah, A. Rao, F. O’Mahony, E. Karl, L. Cheney, I. Rajwani, H. Jain, R. Cortez, A. Chandrasekhar, B. Kanthi, R. Koduri
Ponte Vecchio enables the next generation of HPC/AI workloads and is implemented using the Foveros active 3D logic-on-logic stacking technology along with EMIB. It incorporates over 100B transistors spread across 47 functional tiles and 5 process nodes to enable the Aurora Supercomputer. The paper describes innovations in architecture, design, process, packaging, circuits, die-to-die I/O, power delivery, thermals, test, and CAD to enable the third dimension of Moore’s law scaling.
- Sapphire Rapids: A multi-die Xeon® Scalable Processor
N. Nassif, A. Munch, C. Molnar, G. Pasdast, O. Mendoza, S. Kandula, S. Iyer, Z. Yang, M. Huddart, S. Venkataraman, R. Marom, A. Kern, B. Bowhill, D. Mulvihill, S. Nimmagadda, V. Kalidindi, J. Krause, M. Haq, R. Sharma, K. Duda
Sapphire Rapids (SPR) features increased core counts, greater than 100MB shared L3 cache, DDR5 memory, 32GT/s PCIe/CXL lanes, 16GT/s UPI lanes, and integrated accelerators supporting AI, crypto, compression, and data streaming. To deliver high core counts, IO BW, performance, and improved yield, SPR introduces the concept of a quasi-monolithic: 4 interconnected die with aggregate area beyond the reticle limit. The new die-to-die interconnect over EMIB is introduced.
- Bonanza Mine: An Ultra-low Voltage Energy-efficient Bitcoin Mining ASICs
Suresh, C. Katta, S. Rajagopalan, T. Zhou, A. Patel, R. Rakha, N. Gopalakrishna, S. Mathew, A. Hukkoo
This early version of a blockchain accelerator is a mining specific ASIC with circuit innovations featuring: Bitcoin*-optimized look-ahead message-digest datapath resulting in Cdyn reduction compared to conventional SHA256 digest datapath; half-frequency scheduler datapath reducing sequential and clock power.
- An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS
Kumar, V. Suresh, M. Anders, S. Hsu, A. Agarwal, V. De, S. Mathew
This accelerator’s reconfigurable AES design provides the ability to rapidly switch to a provably secure mode (MTD > 1 Billion power/EM traces) when a side-channel attack is detected while providing up to 2.2x higher AES performance during the safe modes of operation in trusted environments.
- A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation
Y. Segal, A. Laufer, A. Khairi, Y. Krupnik, M. Cusmai, I. Levin, A. Gordon, Y. Sabag, V. Rahinski, G. Ori, N. Familia, S. Litski, T. Warshavsky, U. Virobnik, Y. Horwitz, A. Balankutty, S. Kiran, S. Palermo, P. M. Li, A. Cohen
This power-efficient receiver targets next-generation Ethernet. Doubling the data rate while keeping the same modulation requires doubling the bandwidth and lowering halving both the clocking jitter and circuit noise. These new constraints are met by using a hybrid Continuous Time Linear Equalizer (CTLE).
- A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm
B. Zand, M. Bichan, A. Mahmoodi, M. Shashaani, J. Wang, R. Shulyzki, J. Guthrie, K. Tyshchenko, J. Zhao, E. Liu, N. Soltani, A. Freeman, R. Anand, S. Rubab, R. Khela, S. Sharifian, K. Herterich
This receiver achieves pre-FEC BER<10 4 over dynamic temperature variation of -20C to 105C in a 10nm process technology and channel insertion loss of 5-33dB compliant with the Ethernet standard. Receiver area is 0.14 mm2 and power at 58.125Gbps is 259mW from 1V and 1.8V supplies.
- A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications
B. Khamaisi, D. Ben-Haim, A. Nazimov, A. Ben-Bassat, S. Gross, N. Shay, G. Asa, V. Spector, Y. Eilat, A. Azam, E. Borokhovich, I. Shternberg, P. Skliar, E. Solomon, A. Beidas, T. A. Hazira, A. Lane, E. Shaviv, G. Nudelman, E. Dahan, M. Shemer, N. Kimiagarov, A. Ravi, O. Degani
This reliability-aware circuit topology addresses the challenges of implementation on the more advanced 16nm finFET process node. To the best of the authors’ knowledge, this is the first high power, low voltage polar-DTX demonstrated in 16nm finFET technology.
- A 12 A Imax, Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50 MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS
C. Schaef, T. Salus, R. Rayess, S. Kulasekaran, M. Manusharow, K. Radhakrishnan, J. Douglas
This fully integrated voltage regulator (FIVR) features a digitally assisted control loop that allows autonomous phase shedding (APS) while retaining the transient response of a high-speed analog Type III controller. A magnetic layer that surrounds serially connected plated through-hole vias through the package core increases inductance compared to air core inductors used in previous work.
- A Fully Integrated 160Gb/s D-Band Transmitter with 1.1pJ/b Efficiency in 22nm FinFET
S. Callender, A. Whitcombe, A. Agarwal, R. Bhat, P. Sagazio, G. Dogiamis, B. Carlton, M. Chakravorti, S. Pellerano, C. Hull, M. Rahman, C. Lee
This fully integrated D-band transmitter (TX) achieves 160Gb/s at ~1pJ/b efficiency in 22nm FinFET technology. To the Authors’ knowledge, this TX achieves the highest data rate among published works; performance achieved while integrating all critical blocks, from bits to RF.
- A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup
S. Kundu, T. Huusari, H. Luo, A. Agrawal, S. Shahraini, E. Alban, S. Pellerano, T. Xiong, J. Mix, N. Kurd, M. Abdelmoneum, D. Lake, B. Carlton
This voltage interpolation (VI) technique eliminates voltage reference and associated complex calibration logic, providing fast phase locking, minimal noise, and enhanced fractional frequency synthesis resolution.
- A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer
X. Liu, H. Krishnamurthy, R. Liu, K. Ravichandran, Z. Ahmed, N. Desai, N. Butzen, J. Tschanz, V. De
This Triode Region analog LDO (TRLDO) does not require the power FET to always operate in the saturation region. The TRLDO implements distributed gain stages to mitigate triode region power FET degradation, incorporates an active feedforward 2 ripple shaping technique, and tracks dynamic load current to maintain high PSR across a wide range of frequencies and currents.
Forum Presentations and Tutorial
F1: We’ve Rethought Our Commute; Can We Rethink Our Data’s Commute?
F4: 224 Gb/s Transceiver, End-to-End Channels, and Standardizations
F5: Graphs: Powerful but Hard to Beat
F6: Microarchitectural Vulnerabilities: Evolving Landscape
T9: Design Methodologies for Energy Harvesting Wireless Sensor Nodes
Collaborative Papers and Demos with Universities
- Electronic THz Pencil Beam Forming and 2D Steering for High Angular-Resolution Operation: A 98×98-Unit 265GHz CMOS Reflectarray with In-Unit Digital Beam Shaping and Squint Correction
- A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoMA in 22nm FinFET
- A CMOS Cellular Interface Array for Digital Physiology Featuring High-Density Multi-Modal Pixels and Reconfigurable Sampling Rate
- DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware
- A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend with Self-DOA Correction Adaptive Beamformer
Panel Discussion with Industry Experts
- The Bright and Dark Side of Artificial Intelligence (AI)