Ubiquitous compute, pervasive connectivity, artificial intelligence and cloud-to-edge infrastructure drive a diverse and expanding range of computing workloads from the desktop to the data center.
At Architecture Day 2021, Intel detailed the company’s architectural innovations to meet this exploding demand, setting the stage for new generations of leadership products. Intel architects provided details on two new x86 central processing unit architectures; Intel’s first performance hybrid architecture and Intel® Thread Director; Intel’s next-generation data center processors; infrastructure processing unit architectures; and upcoming graphics architectures.
News
- Raja Koduri Editorial: Intel Advances Architecture for Data Center, HPC-AI and Client Computing
- Fact Sheet: Intel Unveils Biggest Architectural Shifts in a Generation for CPUs, GPUs and IPUs
- Stuart Pann Editorial: Expanding Intel’s Foundry Partnerships: A Critical Piece of IDM 2.0
Event Replay
Video Chapters
x86 Architectures: With its Efficient-core and its Performance-core, Intel signals the biggest architectural shift in a generation for x86 central processing units. The Efficient-core microarchitecture is designed for throughput efficiency and efficient offloading of background tasks for multitasking. It runs at low voltage and creates headroom to increase frequency and ramp up performance for more demanding workloads. The Performance-core microarchitecture is designed for speed, the highest performing CPU core Intel has built. It pushes the limits of low latency and single-threaded application performance and provides a significant boost at high-power efficiency that can better support large applications.
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Client Computing – “Alder Lake,” Intel Thread Director: Intel’s next-generation client architecture, code-named “Alder Lake,” is Intel’s first performance hybrid architecture. Alder Lake integrates a Performance-core and an Efficient-core to provide significant performance across all workload types. For the cores to work seamlessly with the operating system, Intel developed Intel® Thread Director. Built directly into the core, Thread Director empowers the operating system to place the right thread on the right core at the right time. Alder Lake will deliver performance that scales to support all client segments from ultra-portable laptops to enthusiast and commercial desktops.
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Client Computing – Graphics: Xe-HPG is a new discrete graphics microarchitecture for gamers and creators designed for scalability and enthusiast-class performance with a software-first approach. Products based on this microarchitecture will come to market in the first quarter of 2022 under the Intel® Arc™ brand and Alchemist family of system-on-chips.
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Data Center – Sapphire Rapids: Combining Intel’s Performancecores with new accelerator cores, “Sapphire Rapids,” the next generation of Intel® Xeon® Scalable processors, represents the industry’s biggest data center platform advancement in over a decade. The processor delivers substantial compute performance across dynamic and increasingly demanding data center usages and is workload-optimized to deliver high performance on elastic compute models like cloud, microservices and artificial intelligence.
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Data Center – Infrastructure Processing Unit: The IPU is designed to enable cloud and communication service providers to reduce overhead and free up performance for central processing units. Among the new IPU architectures: Mount Evans is Intel’s first ASIC IPU, designed to address the complexity of diverse and dispersed data centers. Oak Springs Canyon is an IPU reference platform built with the Intel® Xeon® D processor and the Intel® Agilex™ FPGA. And the Intel® N6000 Accelerated Development Platform is designed for use with Xeon-based servers.
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Data Center – Ponte Vecchio: Based on the Xe-HPC microarchitecture, Ponte Vecchio delivers industry-leading FLOPs and compute density to accelerate artificial intelligence, high performance computing and advanced analytics workloads. Intel disclosed details of the Xe-HPC microarchitecture, including that A0 silicon performance is providing greater than 45 TFLOPS FP32 throughput, greater than 5 TBps memory fabric bandwidth and greater than 2 TBps connectivity bandwidth.
Presentation Images
Ponte Vecchio: Delivering industry-leading FLOPs and compute density to accelerate artificial intelligence, high performance computing and advanced analytics workloads, the new Xe-HPC microarchitecture is built for scalability. Designed to take advantage of the most advanced silicon technologies, it is built using five process nodes. It is a great example of Intel’s ability to combine multiple process technologies – both internal and external – with advanced packaging technologies to uniquely tailor products to customer and market needs. (Credit: Intel Corporation)
Xe-cores: Intel's Xe-cores include efficient arithmetic units, caches and load/store logic. The arithmetic units include engines for traditional floating point and integer vector operations along with engines to accelerate convolution and matrix operations commonly found in artificial intelligence workloads. Xe-cores include 16 vector engines and 16 matrix engines, which Intel refers to as XMX or Xe Matrix eXtensions. (Credit: Intel Corporation)
Mount Evans: Intel’s first ASIC infrastructure processing unit has been architected and developed hand-in-hand with a top cloud provider. Hyperscale-ready, Mount Evans integrates lessons from multiple generations of FPGA SmartNICs and offers high-performance network and storage virtualization offload while maintaining a high degree of control. (Credit: Intel Corporation)
Oak Springs Canyon: Intel's infrastructure processing unit reference platform is built with Intel XeonD and Intel Agilex FPGA, the industry's leading FPGA in power, efficiency and performance. (Credit: Intel Corporation)
Arrow Creek: Arrow Creek is a SmartNIC adapter that can flexibly accelerate several infrastructure workloads like Juniper Contrail, OVS and SRv6. Designed for use with Intel Xeon-based servers, this acceleration development platform features Intel’s Agilex FPGA, which is the industry’s leader in power, efficiency and performance, and the Intel Ethernet 800 Series controller for high-performance 100G connectivity. (Credit: Intel Corporation)
Sapphire Rapids: Combining Intel's Performance-cores with new accelerator cores, Sapphire Rapids sets the standard for next-generation data center processors. At the heart of Sapphire Rapids is a tiled, modular system-on-chip architecture that delivers significant scalability while maintaining the benefits of a monolithic central processing unit interface thanks to Intel's embedded multi-die interconnect bridge packaging technology. (Credit: Intel Corporation)
Alder Lake SoC: Reinventing the multicore architecture, Alder Lake will be Intel's first performance hybrid architecture with new Intel Thread Director. This is Intel's most intelligent client system-on-chip architecture featuring a combination of Efficient-cores and Performance-cores, scaling from ultra-mobile to desktop, and leading the industry transition with industry leading I/O and memory. (Credit: Intel Corporation)
Thread Director: Intel's unique approach to scheduling was developed to ensure Efficient-cores and Performance-cores work seamlessly together, dynamically and intelligently assigning workloads from the start and optimizing the system for maximum real-world performance and efficiency. Intelligence built directly into the core, Thread Director works seamlessly with the operating system to place the right thread on the right core at the right time. (Credit: Intel Corporation)
Event Images
Raja Koduri, Intel senior vice president and general manager of the Accelerated Computing Systems and Graphics Group, displays a wafer with Intel Arc high-performance discrete graphics hardware as part of a presentation during Intel Architecture Day 2021. The virtual event was held in August 2021. (Credit: Intel Corporation)
Masooma Bhaiwala, Intel vice President in the Accelerated Computing Systems & Graphics Group and general manager of the Discrete Graphics SoCs Group, displays Ponte Vecchio as part of a presentation during Intel Architecture Day 2021. The virtual event was held in August 2021. (Credit: Intel Corporation)
Guido Appenzeller, chief technology officer in Intel's Data Platforms Group, displays an infrastructure processing unit as part of a presentation during Intel Architecture Day 2021. The virtual event was held in August 2021. (Credit: Intel Corporation)
Naru Sundar, principal engineer and lead architect in Intel’s Ethernet Platforms Group, holds an infrastructure processing unit as part of a presentation during Intel Architecture Day 2021. The virtual event was held in August 2021. (Credit: Intel Corporation)
Sailesh Kottapalli, Intel Senior Fellow in the Design Engineering Group and chief architect in the Datacenter Processor Architecture Group, holds a Sapphire Rapids chip as part of a presentation during Intel Architecture Day 2021. The virtual event was held in August 2021. (Credit: Intel Corporation)
Demos
Xe HPG – High Quality Super Sampling: This XeSS demo in 4K shows high-quality super sampling in action on Xe HPG. XeSS uses deep learning to synthesize images that are very close to the quality of native high-res rendering. This reconstruction is performed by a neural network trained to deliver high performance and great quality. The contents and game levels shown in this demo were created by Rens. Rens is a 3D artist, environment artist and technical art director. He is known for his outstanding photogrammetry techniques and high-end rendering skills, and has worked with top game development studios like DICE, Epic Games and Sony.
Intel® oneAPI Rendering Toolkit: This demo shows an end-to-end film quality creator workflow using a pre-production implementation of Intel® Embree and artificial intelligence-based Intel® Open Image Denoise libraries from the open-source Intel® oneAPI Rendering Toolkit running cross-architecture on CPUs and Xe architecture ray tracing-accelerated GPUs. This includes a look at a CPU-based creator workflow using the commercial SideFx Houdini application with Pixar’s open-source USD APIs calling the Embree and Open Image Denoise APIs. Then using the same USD, Embree and Open Image Denoise API’s call on the CPU to deliver beautiful rendering in real time via an Xe GPU. Experience a real-time walk-through of an Intel history-inspired path traced scene at the fictitious 4004 Moore Lane. Finally, see the final 4K film-quality version of a 45-second film containing 1,350 frames rendered many times faster than with the CPU only. Now, the same feature-rich render kit capabilities artists and app developers crave on CPUs, including ray tracing and AI acceleration, are available on GPUs.
Intel® oneAPI AI Analytics Toolkit: This demo highlights Ponte Vecchio with Intel® oneAPI AI Analytics Toolkit running ResNet50 benchmarks. Early results from ResNet50 inference and training throughput when using Ponte Vecchio and Sapphire Rapids have already established a new performance bar and show that Intel is on track to deliver its goal of artificial intelligence and high performance computing performance leadership that surpasses the previous performance leader.
AMX: Advanced matrix extensions (AMX) is Intel’s next-generation, built-in AI acceleration advancement for machine learning inference and training, targeted for data center. AMX is a hardware block in the Sapphire Rapids CPU with a new expandable two-dimensional register file and new matrix multiply instructions to enhance performance for a variety of deep learning workloads. Demo shows AMX in action in Intel’s validation labs.
Alder Lake: This demo shows several examples of Intel Thread Director technology running on an Alder Lake platform with Microsoft Windows 11. Intel Thread Director provides hints to the operating system for optimally scheduling threads of various types to run on either a Performance-core or an Efficient-core. Thread Director technology allows Intel to provide smarter assistance to the operating system by monitoring the instruction mix, the current state of each core and other relevant microarchitecture telemetry at a granular level.