Active Parallel Configuration

You can perform active parallel (AP) configuration using a supported common flash interface (CFI) parallel flash memory. During AP configuration, the Altera® device is the master and the parallel flash memory is the slave. Configuration data is transferred to the Altera device on the DATA[15:0] pins. This configuration data is synchronized to the DCLK input. Configuration data is transferred at a rate of 16 bits per clock cycle. The DCLK frequency driven out by the Altera device during AP configuration is approximately 40 MHz.

For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook.

Configuration Method

  • Using a supported common flash interface (CFI) parallel flash memory

Application Note

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