Description
The Quartus® II software does not officially support importing Verilog netlists generated from Synopsys Design Compiler.
The Quartus II software may generate errors during compilation when Design Compiler is set as the synthesis tool and the Library Mapping File (.lmf) is specifed via the EDA Tools Settings menu.
To solve this issue, set the Library Mapping File altsyn.lmf by following these steps:
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Choose Settings from the Assignments menu.
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Under Analysis & Synthesis Settings, choose Verilog HDL Input.
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Enter the path to your Library Mapping File altsyn.lmf in the Library Mapping File box.
The altsyn.lmf file can be found in the Quartus II installation directory: <Quartus II Installation Path>\quartus\lmf.