Performing a Timing Simulation with the Incisive Enterprise Simulator Software
Parent topic: Performing a Timing Simulation with the Incisive Enterprise Simulator Software Previous topic: To perform a timing simulation of a Verilog HDL design with command-line commands Next topic: To perform a timing simulation of a VHDL design with command-line commands

To perform a timing simulation of a VHDL design with the IES GUI

  1. If you have not already done so, perform Setting Up the Incisive Enterprise Simulator Working Environment.
  2. Start the IES software by typing nclaunch at a command prompt:
  3. On the File menu, click Set Design Directory.
  4. Browse to your design directory.
  5. Click Create cds.lib File. In the New cds.lib File dialog box, select the libraries to include and click Save.
  6. Under Work Library, click New.
    Note: Altera recommends using the IES (Verilog or VHDL) default library names when you create a library. You should name the IES software libraries as follows:
    • When you run the IES software independently from the Quartus® Prime Standard Edition software, you should name your library work.
    • When you run the IES software automatically from the Quartus® Prime Standard Edition software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate level simulation.
  7. Specify your new work library name; for example, type work.
  8. Click OK.
  9. Repeat steps 7 and 8 for each functional simulation library; for example, for other work library names, you could type lpm, altera_mf, altera.
  10. In the Set Design Directory dialog box, click OK.
  11. In the Library Browser, right-click the files you want to compile, and then click NCVhdl on the pop-up menu.
  12. In the Compile VHDL dialog box, you will see a list of all of the files you selected. Apply any wanted options, and then click OK.
  13. Repeat steps 12 and 13 to compile the VHDL Output File for the project and the appropriate library model files.
  14. To simulate the design, click Simulator and type <work library>.<top-level entity name> in the Design Unit text box.

To direct the IES software to generate a Value Change Dump File that you can then use to perform power analysis in the Quartus® Prime Standard Edition PowerPlay Power Analyzer:

  1. In the file explorer pane, select the <testbench or design instance name>_dump_all_vcd_nodes.tcl Tcl Script File (.tcl) generated by the Quartus® Prime Standard Edition EDA Netlist Writer.
  2. On the File menu, click Source. The Tcl Script File directs the IES software to monitor and write the output signals contained in the Tcl Script File to a Value Change Dump File during simulation.
Related information

Setting Up the Incisive Enterprise Simulator Working Environment
Altera Simulation Models
Parent topic: Performing a Timing Simulation with the Incisive Enterprise Simulator Software Previous topic: To perform a timing simulation of a Verilog HDL design with command-line commands Next topic: To perform a timing simulation of a VHDL design with command-line commands

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