Altera provides the following simulation model files located in the \quartus\eda\sim_lib directory, for use with supported EDA simulators. Logical library names that
end with "_ver" are for Verilog HDL designs.
Important: You can use NativeLink or the Simulation Library Compiler to automatically compile the appropriate simulation model files for your design.
Note: Only ModelSim or QuestaSim version 6.6c and later can read Quartus® Prime Standard Edition software version 10.1 and later IEEE encrypted simulation model files. You can simulate Mentor Graphics Verilog HDL
models in any single language Verilog HDL, VHDL, or mixed language version of ModelSim or QuestaSim. Mentor Graphics single and mixed language simulators consume one simulator license when
you simulate a VHDL design containing encrypted Verilog HDL models. Similarly, version 10.1 and later simulation model files that are IEEE encrypted for Aldec, Cadence, or Synopsys simulators,
can be read only by the corresponding simulator. These encrypted simulation models are located in the /quartus/eda/sim_lib/<simulator> directory.
Some Altera IP cores provide additional encrypted models in the <simulator>subdirectories where your IP variant's simulation models are
generated.
Note: For more information about compiling simulation models, refer to
Preparing for
Simulation.