Performing a Timing Simulation with the Incisive Enterprise Simulator Software

The following sections demonstrate how to perform a timing simulation of a Quartus® Prime Standard Edition-generated Verilog Output File (.vo) Definition and the corresponding Standard Delay Format Output File (.sdo) Definition with the Cadence Incisive Enterprise Simulator (IES) software:

Note: For more information about using EDA simulators, refer to Cadence Incisive Enterprise Simulator Support in the Quartus® Prime Standard Edition Handbook.

If you want to perform power analysis, perform power analysis with the PowerPlay Power Analyzer.

  1. To perform a timing simulation of a Verilog HDL design with the IES GUI
  2. To perform a timing simulation of a Verilog HDL design with command-line commands
  3. To perform a timing simulation of a VHDL design with the IES GUI
  4. To perform a timing simulation of a VHDL design with command-line commands

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