Perform a Gate-Level Simulation

If you have not already done so, specify the settings to generate netlist files.
1. To generate post-synthesis simulation netlist files:
  1. Perform Analysis and Synthesis. On the Processing menu, point to Start and click Start Analysis and Synthesis (you can also perform this after step 2).
  2. Turn on the Generate Netlist for Functional Simulation Only option by performing the following steps:
    1. On the Assignments menu, click EDA Tool Settings.
    2. In the Category list of the EDA Tool Settings page, click Simulation.
    3. In the Tool name list, select Active-HDL.
    4. Under EDA Netlist Writer settings, in the Format for output netlist list, select VHDL. You can also modify where you want the post-synthesis netlist generated by editing or browsing to a directory in the Output directory box.
    5. Click More EDA Netlist Writer Settings. The More EDA Netlist Writer Settings dialog box appears. In the Existing options settings list, click Generate netlist for functional simulation only and select On from the Setting list under Options.
    6. Click OK.
    7. In the Settings dialog box, click OK.
  3. On the Processing menu, point to Start and click Start EDA Netlist Writer.
2. To generate gate-level timing simulation netlist files:
  1. On the Assignments menu, click EDA Tool Settings.
  2. In the Category list, in the EDA Tool Settings page, click Simulation.
  3. In the Tool name list, select Active-HDL.
  4. Under EDA Netlist Writer options, in the Format for output netlist list, select VHDL. You can also modify where you want the post-synthesis netlist generated by editing or browsing to a directory in the Output directory box.
  5. Click OK.
  6. In the Settings dialog box, click OK.
  7. If you have not run a full compilation, perform a full compilation. On the Processing menu, click Start Compilation.
  8. If you have already run a full compilation, run the EDA Netlist Writer. On the Processing menu, point to Start and click Start EDA Netlist Writer.
  During the Full compilation or EDA Netlist Writer stage, the Quartus^® Prime Standard Edition software produces a VHDL Output File (.vho) Definition and a Standard Delay Format Output File (.sdo) Definition used for gate-level timing simulations in the Active-HDL software. The output netlist file is mapped to architecture-specific primitives. Timing information for the netlist is included in the Standard Delay Format Output File (.sdo). The resulting netlist is located in the output directory you specified in the Settings dialog box, which defaults to <project directory>/simulation/activehdl.
  
  Note:
  The EDA Netlist Writer generates a functional simulation netlist rather than a timing simulation netlist for designs that specify the StratixV or newer device families, even if you specified a timing simulation netlist.
To verify that pre-existing libraries are not attached in the Active-HDL software:
1. On the View menu, click Library Manager. The Library Manager window appears.
2. Check to see that the simulation libraries are present, for example, altera_mf.
3. If simulation libraries are present for your version of the Quartus^® Prime Standard Editionsoftware, you can skip to step 5. Otherwise, you can download the appropriate library files from the Aldec website or create them manually with steps 3 and 4.
To create a workspace in the Active-HDL software and compile simulation libraries:
1. On the File menu, point to New and click Design. The New Design Wizard appears.
2. Select Create an Empty Design and keep the Create New Workspace option selected.
3. Click Next. The Property page appears. In the Property page, click Next.
4. Type the name in the Design name and Library name fields, for example, stratixiii. Select the location of your design in the Design folder field, and click Next. Altera recommends that you use the same name for the design and the library.
5. Click Finish to complete the wizard.
6. On the Design menu, click Add files to Design.
7. Browse to <Quartus^® Prime Standard Edition installation directory>/eda/sim_lib and add the necessary simulation model files. For example, compile the stratixiii_atoms.vhd and stratixiii_atoms_components.vhd model files into the stratixiii library.
8. On the Design menu, click Compile All to compile all the files and add them to the design library, for example, stratixiii_atoms.vhd and stratixiii_atoms_components.vhd.
9. On the File menu, click Close Workspace.
You must map the created library in the Active-HDL software. To map simulation libraries:
1. On the View menu, click Library Manager. The Library Manager window appears.
2. On the Library menu, click Attach Library.
3. Locate the .lib file, for example, stratixiii.lib, from the design directory that you created in the previous steps and click Open.
4. To attach the simulation library as a global library inside your library manager and make it visible for any design in the Active-HDL software, turn on Attach as global library.
To create a workspace in the Active-HDL software and compile your test bench and design files into the work library:
1. On the File menu, point to New and click Design. The New Design Wizard appears.
2. Select Create an Empty Design and keep the Create New Workspace option selected.
3. Click Next. The Property page appears. In the Property page, click Next to proceed to the Design name and Library name fields.
4. Type work for the design name and select the location of your design. Altera recommends that you use same name for your the design and the library.
5. Click Finish to complete the wizard.
6. On the Design menu, click Add files to Design.
7. Browse to the VHDL output file directory, for example, <project_directory>/simulation/activehdl, and add the VHDL Output File and Standard Delay Format Output File.
8. Browse to the testbench directory and add the testbench file.
9. On the Design menu, click Compile All to compile the testbench and VHDL output netlist files.
To load a design in the Active-HDL software, click Settings. The Design Settings dialog box appears. Expand the Simulation category and click SDF.
Note: If there are no Standard Delay Format Output files listed, none have been added to the design. You must add the Standard Delay Format Output file before running the timing simulation.
In the Files-Region dialog box, select the level of the design hierarchy to which the Standard Delay Format Output Files (.sdo) should be bonded to. For example, if your design under test is instantiated in the testbench file under the i1 label, the region should be 'i1/'.
In the SDF settings box, set Value to Average and set Load to Yes so that the simulator loads this file upon simulation start.
Note: You do not need to set the Value (minimum, average, maximum) for the Standard Delay Format Output because the Quartus^® Prime Standard EditionEDA Netlist Writer generates the Standard Delay Format Output file using the same value for the triplet (minimum, average, and maximum timing values).
Click OK to close the Design Settings dialog box.
To load a design in the Active-HDL software, in the Design Browser, click the Top-level Selection list. Select the top-level module, which is your testbench with corresponding architecture.
To initialize simulation in the Active-HDL software, on the Simulation menu, click Initialize Simulation. This loads the simulation. The Design Browser automatically switches to the Structure tab and displays the design tree.
To perform the simulation in the Active-HDL software:
1. On the File menu, point to New and click Waveform.
2. Drag signals of interest from the Structure tab of the Design Browser to the Waveform window.
3. On the Simulation menu, click Run Until.
4. In the pop-up window, specify how long you want your simulation to run, for example, 500 ns.