You can use Altera-provided megafunctions in other EDA tools by using the IP Catalog to create and instantiate custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions, as well as Altera megafunctions.
The following examples show how to create a VerilogHDL or VHDL design using the specified EDA tools. Although one example is provided for each tool and each type of megafunction, you can use the same procedures and principles to create similar designs for other megafunctions or other EDA tools.
For information on how to use the following functions, refer to the topics listed in the following table:
Function |
Language |
EDA Tool |
Topic Title |
---|---|---|---|
altclklockClockLock phase-locked loop (PLL) |
VerilogHDL |
Synplify |
Creating and Instantiating a Verilog HDL Function for Use with the Synplify Software |
altclklockClockLock phase-locked loop (PLL) |
VHDL |
Synplify |
Creating and Instantiating a VHDL Function for Use with the Synplify Software |