Creating and Instantiating a VHDL Function for Use with the Synplify Software

You can create or modify design files that contain custom megafunction variations of Altera-provided functions. You can then instantiate the custom megafunction variations in a design file for use with the Synopsys Synplify and Quartus® Prime Standard Edition software. This procedure shows only how to instantiate a ClockLock PLL function using VHDL; however, you can use similar procedures to instantiate other Altera-provided functions.

  1. If you have not already done so, set up the Synplify working environment.
  2. If you have not already done so, create a design for use with the Synplify software.
  3. Open the IP Catalog and specify appropriate options for the megafunction you want to instantiate.
  4. The IP Catalog generates custom megafunction variations that are based on Altera-provided functions, including library of parameterized modules (LPM) functions, as well as Altera megafunctions.
  5. If necessary, perform a functional simulation of the design using an EDA simulation tool. Refer to the following example for a sample script used in performing a functional simulation:
    • Example of Performing a Functional Simulation of a Synplify VHDL Design with a Custom Megafunction Variation with the ModelSim Software
  6. Generate Verilog Quartus mapping files with the Synplify software.
  7. If you have not already done so, create a new project or open an existing project.
  8. Compile the design in the Quartus® Prime Standard Edition software.
  9. If necessary, perform a timing simulation with the ModelSim software or simulate the design with another Verilog HDL simulation tool. Refer to the following example for a sample script that you can use to perform the timing simulation:
Related concepts

About the IP Catalog and Parameter Editor
Related tasks

Setting Up the Synplify Working Environment
Creating a Design for Use with the Synplify Software
Performing a Timing Simulation with the ModelSim Software
Related reference

Megafunctions/LPM
Example of Creating a Black Box for a VHDL Custom Variation of a Megafunction with the Synplify Software
Example of Performing a Functional Simulation of a Synplify VHDL Design with a Custom Megafunction Variation with the ModelSim Software
Example of Performing a Timing Simulation of a Synopsys VHDL Design with a Custom Megafunction Variation with the ModelSim Software

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