You can create VerilogHDL design files with the Quartus® Prime Standard Edition Text Editor or another standard text editor for use with the Synopsys Synplify software.
To create a Verilog HDL or VHDL design for use with the Synplify software:
When connecting ports in the Verilog Design File (.v) Definition , make sure you connect ports by name instead of by order. When generating Verilog Output File (.vo) Definition from imported VQM Files for simulation in other EDA simulation tools, the Quartus® Prime Standard Edition software does not retain the order of ports.
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