Creating and Instantiating a Verilog HDL Function for Use with the Synplify Software

You can create or modify design files that contain custom megafunction variations of Altera-provided functions. You can then instantiate the custom megafunction variations in a design file for use with the Synopsys Synplify and Quartus® Prime Standard Edition software. This procedure shows only how to instantiate a ClockLock PLL function using Verilog HDL; however, you can use similar procedures to instantiate other Altera-provided functions.

  1. If you have not already done so, set up the Synplify Working environment.
  2. If you have not already done so, create a design for use with the Synplify software.
  3. Open the IP Catalog and specify appropriate options for the megafunction you want to instantiate.
  4. To prepare the Verilog HDL design for synthesis with the Synplify software, you must specify that the Synplify software should treat the design file created in the MegaWizard Plug-In Manager as a "black box." The Synplify software then makes the correct connections to the ports in the Verilog HDL output netlist file (.vqm). The Quartus® Prime Standard Edition software reads in the Verilog HDL netlist file as a Verilog Quartus Mapping File (.vqm) Definition and processes the instantiated megafunction. The MegaWizard Plug-In Manager also generates a file with the extension _bb.v that can be used as an empty module declaration for use as a black box. To specify that the Synplify software should treat the design file for the megafunction as a "black box," refer to the following example:
    • Example of Creating a Black Box for a Verilog HDL Custom Variation of a Megafunction with the Synplify Software
    Note:

    The design file generated by the IP Catalog must be in the same directory as the VQM File or added to the Quartus® Prime Standard Edition project.

  5. If necessary, perform a functional simulation of the design using an EDA simulation tool. Refer to the following example for instructions and a sample script used to perform a functional simulation:
    • Example of Performing a Functional Simulation of a Synplify Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software
  6. Generate Verilog Quartus mapping files with the Synplify software.
  7. If you have not already done so, create a new project or open an existing project.
  8. Compile the design in the Quartus® Prime Standard Edition software.
  9. If necessary, perform a timing simulation with the ModelSim software or simulate the design with another Verilog HDL simulation tool. Refer to the following example for instructions and a sample script used in performing the timing simulation:
Related concepts

About the IP Catalog and Parameter Editor
About the Project Navigator
Related tasks

Setting Up the Synplify Working Environment
Creating a Design for Use with the Synplify Software
Performing a Timing Simulation with the ModelSim Software
Related reference

Megafunctions/LPM
Example of Creating a Black Box for a Verilog HDL Custom Variation of a Megafunction
Example of Performing a Functional Simulation of a Synplify Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software
Example of Performing a Timing Simulation of a Synplify Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software

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