Example of Performing a Functional Simulation of a Synplify Verilog HDL Design with a Custom Megafunction Variation with the ModelSim Software

You can perform a functional simulation of the custom megafunction variation you created in Example of Creating a black box for a Verilog HDL Custom Variation of a Megafunction with the Synplify Software before performing compilation in the Synopsys Synplify or the Quartus^® Prime Standard Edition software.

To perform a functional simulation in the ModelSim software, you can create a script that performs the following steps:

• Compiles the altera_mf.v library.
• Compiles the Verilog Design File (.v) Definition generated by the IP Catalog. In this example, the file is my_pll.v.
• Compiles the top-level Verilog Design File. In this example, the file name is pllsource.v.
• Compiles the testbench file. In this example, the testbench file name is plltest.v.

You can simulate this sample design in the ModelSim software by using the commands shown in the following sample script:

            vlib work                                               # Create working directory
vlog /quartus/eda/sim_lib/altera_mf.v                   # Compile the altera_mf library
exec vmap altera_mf work                                # Create altera_mf library and map it to work
vlog my_pll.v                                           # Compile generated megafunction file
vlog pllsource.v                                        # Compile source instantiating module
vlog plltest.v                                          # Compile testbench file
vsim -t ps work.plltest                                 # Simulate plltest with resolution in ps
add wave /plltest/*                                     # Add the port signals to the waveform view
add wave /plltest/U1/PLL_1/altclock_component/clock1    # Add the clock1 altclklock signal to the 
                                                        # waveform view
run 1000 ns                                             # Run the simulation for 1000 ns