spis Address Map

Module Instance Base Address End Address
i_spis_0_spis 0xFFDA2000 0xFFDA2FFF
i_spis_1_spis 0xFFDA3000 0xFFDA3FFF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
ctrlr0 0x0 32 RW 0x7 
Control Register 0:
This register controls the serial data transfer. It is impossible to
write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi
is enabled and disabled by writing to the SSIENR register.
spienr 0x8 32 RW 0x0 
SSI Enable Register
mwcr 0xC 32 RW 0x0 
Microwire Control Register.
This register controls the direction of the data word for the half-duplex
Microwire serial protocol. It is impossible to write to this register
when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by
writing to the SSIENR register.
txftlr 0x18 32 RW 0x0 
Transmit FIFO Threshold Level.
This register controls the threshold value for the transmit FIFO memory.
The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
rxftlr 0x1C 32 RW 0x0 
Receive FIFO Threshold level.
This register controls the threshold value for the receive FIFO memory.
The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.
txflr 0x20 32 RO 0x0 
Transmit FIFO Level Register
rxflr 0x24 32 RO 0x0 
Receive FIFO Level Register
sr 0x28 32 RO 0x6 
Status Register.
This is a read-only register used to indicate the current transfer status,
FIFO status, and any transmission/reception errors that may have occurred.
The status register may be read at any time. None of the bits in this
register request an interrupt.
imr 0x2C 32 RW 0x1F 
Interrupt Mask Register
isr 0x30 32 RO 0x0 
Interrupt Status Register
risr 0x34 32 RO 0x0 
Raw Interrupt StatusRegister
txoicr 0x38 32 RO 0x0 
Transmit FIFO Overflow Interrupt Clear Register
rxoicr 0x3C 32 RO 0x0 
Receive FIFO Overflow Interrupt Clear Register
rxuicr 0x40 32 RO 0x0 
Receive FIFO Underflow Interrupt Clear Register
icr 0x48 32 RO 0x0 
Interrupt Clear Register
dmacr 0x4C 32 RW 0x0 
DMA Control Register.
This register is only valid when DW_apb_ssi is configured with a set of
DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is
not configured for DMA operation, this register will not exist and writing
to the register's address will have no effect; reading from this register
address will return zero. The register is used to enable the DMA
Controller interface operation.
dmatdlr 0x50 32 RW 0x0 
DMA Transmit Data Level.
This register is only valid when the DW_apb_ssi is configured with a set
of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not
configured for DMA operation, this register will not exist and writing
to its address will have no effect; reading from its address will
return zero.
dmardlr 0x54 32 RW 0x0 
DMA Receive Data Level.
This register is only valid when DW_apb_ssi is configured with a set of
DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured
for DMA operation, this register will not exist and writing to its address
will have no effect; reading from its address will return zero.
idr 0x58 32 RO 0x5510005 
Identification Register.
This register contains the peripherals identification code, which is
written into the register at configuration time using coreConsultant.
spi_version_id 0x5C 32 RW 0x3332322A 
coreKit Version ID Register
dr 0x60 32 RW 0x0 
The DW_apb_ssi data register is a 16-bit read/write buffer for the
transmit/receive FIFOs. When the register is read, data in the receive
FIFO buffer is accessed. When it is written to, data are moved into the
transmit FIFO buffer; a write can occur only when SSI_EN = 1. FIFOs are
reset when SSI_EN = 0.
msticr 0x44 32 RO 0x0 
Multi-Master Interrupt Clear Register