rxuicr

         Receive FIFO Underflow Interrupt Clear Register

Module Instance	Base Address	Register Address
`i_spis_0_spis`	`0xFFDA2000`	`0xFFDA2040`
`i_spis_1_spis`	`0xFFDA3000`	`0xFFDA3040`

Offset: 0x40

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`rxuicr` `RO 0x0`

rxuicr Fields

Bit	Name	Description	Access	Reset
0	`rxuicr`	Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxu_intr interrupt; writing has no effect.	`RO`	`0x0`