sr
Status Register.
This is a read-only register used to indicate the current transfer status,
FIFO status, and any transmission/reception errors that may have occurred.
The status register may be read at any time. None of the bits in this
register request an interrupt.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_spis_0_spis | 0xFFDA2000 | 0xFFDA2028 |
| i_spis_1_spis | 0xFFDA3000 | 0xFFDA3028 |
Offset: 0x28
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
txe RO 0x0 |
rff RO 0x0 |
rfne RO 0x0 |
tfe RO 0x1 |
tfnf RO 0x1 |
busy RO 0x0 |
|||||||||
sr Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 5 | txe | Transmission Error. Set if the transmit FIFO is empty when a transfer is started. This bit can be set only when the DW_apb_ssi is configured as a slave device. Datafrom the previous transmission is resent on the txd line. This bit is cleared when read. 0 - No error 1 - Transmission error
|
RO | 0x0 | ||||||
| 4 | rff | Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0 - Receive FIFO is not full 1 - Receive FIFO is full
|
RO | 0x0 | ||||||
| 3 | rfne | Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0 - Receive FIFO is empty 1 - Receive FIFO is not empty
|
RO | 0x0 | ||||||
| 2 | tfe | Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0 - Transmit FIFO is not empty 1 - Transmit FIFO is empty
|
RO | 0x1 | ||||||
| 1 | tfnf | Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0 - Transmit FIFO is full 1 - Transmit FIFO is not full
|
RO | 0x1 | ||||||
| 0 | busy | SSI Busy Flag. When set, indicates that a serial transfer is in progress; when cleared indicates that the DW_apb_ssi is idle or disabled. 0 - DW_apb_ssi is idle or disabled 1 - DW_apb_ssi is actively transferring data
|
RO | 0x0 |