risr

         Raw Interrupt StatusRegister
      
Module Instance Base Address Register Address
i_spis_0_spis 0xFFDA2000 0xFFDA2034
i_spis_1_spis 0xFFDA3000 0xFFDA3034

Offset: 0x34

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rxfir

RO 0x0

rxoir

RO 0x0

rxuir

RO 0x0

txoir

RO 0x0

txeir

RO 0x0

risr Fields

Bit Name Description Access Reset
4 rxfir
Receive FIFO Full Raw Interrupt Status
0 = ssi_rxf_intr interrupt is not active prior to masking
1 = ssi_rxf_intr interrupt is active prior to masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
3 rxoir
Receive FIFO Overflow Raw Interrupt Status
0 = ssi_rxo_intr interrupt is not active prior to masking
1 = ssi_rxo_intr interrupt is active prior masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
2 rxuir
Receive FIFO Underflow Raw Interrupt Status
0 = ssi_rxu_intr interrupt is not active prior to masking
1 = ssi_rxu_intr interrupt is active prior to masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
1 txoir
Transmit FIFO Overflow Raw Interrupt Status
0 = ssi_txo_intr interrupt is not active prior to masking
1 = ssi_txo_intr interrupt is active prior masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
0 txeir
Transmit FIFO Empty Raw Interrupt Status
0 = ssi_txe_intr interrupt is not active prior to masking
1 = ssi_txe_intr interrupt is active prior masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0