fpga_mgr_fpgamgrregs Summary

Base Address: 0xFFD03000

Register Address Offset	Bit Fields
`i_fpga_mgr_fpgamgrregs`
`dclkcnt` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`cnt` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cnt` `RW 0x0`
`dclkstat` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`dcntdone` `RW 0x0`
`gpo` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`gpi` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`misci` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`bootFPGArdy` `RO 0x0`	`bootFPGAfail` `RO 0x0`
`emr_data0` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`emr_data1` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`emr_data2` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`emr_data3` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`emr_data4` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`emr_data5` `0x44`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RO 0x0`
`emr_valid` `0x48`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`vld` `0x0`
`emr_en` `0x4C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`en` `RW 0x0`
`jtag_config` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`txSize` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`tckRatio` `RW 0x14`								`Reserved`			`trstEn` `RW 0x0`	`Reserved`	`loopBackEn` `RW 0x0`	`jtagPortEn` `RW 0x0`	`JtagHostEn` `RW 0x0`
`jtag_status` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`txDoneSize` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`SessionStatus` `0x0`	`Reserved`			`rxFifoFull` `0x0`	`rxFifoEmpty` `0x1`	`txFifoFull` `0x0`	`txFifoEmpty` `0x1`	`rxFifoLevel` `0x0`				`txFifoLevel` `0x0`
`jtag_kick` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`clearRxFifo` `0x0`	`clearTxFifo` `0x0`	`stopSession` `0x0`	`startSession` `0x0`
`jtag_data_w` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`tmsData` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`tdiData` `0x0`
`jtag_data_r` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`tdiData` `0x0`
`imgcfg_ctrl_00` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`s2f_condone_oe` `RW 0x0`	`Reserved`							`s2f_nstatus_oe` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`s2f_nconfig` `RW 0x1`	`Reserved`					`s2f_nenable_condone` `RW 0x1`	`s2f_nenable_nstatus` `RW 0x1`	`s2f_nenable_nconfig` `RW 0x1`
`imgcfg_ctrl_01` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`s2f_nce` `RW 0x1`	`Reserved`							`s2f_pr_request` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`s2f_nenable_config` `RW 0x1`
`imgcfg_ctrl_02` `0x78`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`cfgwidth` `RW 0x0`	`Reserved`						`cdratio` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`en_cfg_data` `RW 0x0`	`Reserved`							`en_cfg_ctrl` `0x0`
`imgcfg_stat` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`		`emr` `RO 0x0`	`jtagm` `RO 0x0`	`Reserved`		`imgcfg_FifoFull` `RO 0x0`	`imgcfg_FifoEmpty` `RO 0x1`	`Reserved`					`f2s_msel2` `RO 0x0`	`f2s_msel1` `RO 0x0`	`f2s_msel0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`f2s_nceo_oe` `RO 0x0`	`f2s_nconfig_pin` `RO 0x0`	`f2s_pr_error` `RO 0x0`	`f2s_pr_done` `RO 0x0`	`f2s_pr_ready` `RO 0x0`	`f2s_cvp_conf_done` `RO 0x0`	`f2s_condone_oe` `RO 0x0`	`f2s_condone_pin` `RO 0x0`	`f2s_nstatus_oe` `RO 0x0`	`f2s_nstatus_pin` `RO 0x0`	`f2s_initdone_oe` `RO 0x0`	`f2s_usermode` `RO 0x0`	`f2s_early_usermode` `RO 0x0`	`f2s_crc_error` `RO 0x0`
`intr_masked_status` `0x84`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`		`emr` `RW 0x0`	`jtagm` `RW 0x0`	`Reserved`		`imgcfg_FifoFull` `RW 0x0`	`imgcfg_FifoEmpty` `RW 0x0`	`Reserved`					`f2s_msel2` `RW 0x0`	`f2s_msel1` `RW 0x0`	`f2s_msel0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`f2s_nceo_oe` `RW 0x0`	`f2s_nconfig_pin` `RW 0x0`	`f2s_pr_error` `RW 0x0`	`f2s_pr_done` `RW 0x0`	`f2s_pr_ready` `RW 0x0`	`f2s_cvp_conf_done` `RW 0x0`	`f2s_condone_oe` `RW 0x0`	`f2s_condone_pin` `RW 0x0`	`f2s_nstatus_oe` `RW 0x0`	`f2s_nstatus_pin` `RW 0x0`	`f2s_initdone_oe` `RW 0x0`	`f2s_usermode` `RW 0x0`	`f2s_early_usermode` `RW 0x0`	`f2s_crc_error` `RW 0x0`
`intr_mask` `0x88`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`		`emr` `RW 0x1`	`jtagm` `RW 0x1`	`Reserved`		`imgcfg_FifoFull` `RW 0x1`	`imgcfg_FifoEmpty` `RW 0x1`	`Reserved`					`f2s_msel2` `RW 0x1`	`f2s_msel1` `RW 0x1`	`f2s_msel0` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`f2s_nceo_oe` `RW 0x1`	`f2s_nconfig_pin` `RW 0x1`	`f2s_pr_error` `RW 0x1`	`f2s_pr_done` `RW 0x1`	`f2s_pr_ready` `RW 0x1`	`f2s_cvp_conf_done` `RW 0x1`	`f2s_condone_oe` `RW 0x1`	`f2s_condone_pin` `RW 0x1`	`f2s_nstatus_oe` `RW 0x1`	`f2s_nstatus_pin` `RW 0x1`	`f2s_initdone_oe` `RW 0x1`	`f2s_usermode` `RW 0x1`	`f2s_early_usermode` `RW 0x1`	`f2s_crc_error` `RW 0x1`
`intr_polarity` `0x8C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`		`emr` `RW 0x1`	`jtagm` `RW 0x1`	`Reserved`		`imgcfg_FifoFull` `RW 0x1`	`imgcfg_FifoEmpty` `RW 0x1`	`Reserved`					`f2s_msel2` `RW 0x1`	`f2s_msel1` `RW 0x1`	`f2s_msel0` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`		`f2s_nceo_oe` `RW 0x1`	`f2s_nconfig_pin` `RW 0x1`	`f2s_pr_error` `RW 0x1`	`f2s_pr_done` `RW 0x1`	`f2s_pr_ready` `RW 0x1`	`f2s_cvp_conf_done` `RW 0x1`	`f2s_condone_oe` `RW 0x1`	`f2s_condone_pin` `RW 0x1`	`f2s_nstatus_oe` `RW 0x1`	`f2s_nstatus_pin` `RW 0x1`	`f2s_initdone_oe` `RW 0x1`	`f2s_usermode` `RW 0x1`	`f2s_early_usermode` `RW 0x1`	`f2s_crc_error` `RW 0x1`
`dma_config` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`															`clearFifo` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dmareq_enable` `0x0`	`dmareq_level` `0x0`
`imgcfg_fifo_status` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`FifoEmpty` `0x1`	`FifoFull` `0x0`	`FifoLevel` `0x0`