imgcfg_fifo_status

         Consist of control bit and status information.

Module Instance	Base Address	Register Address
`i_fpga_mgr_fpgamgrregs`	`0xFFD03000`	`0xFFD03094`

Offset: 0x94

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`FifoEmpty` `0x1`	`FifoFull` `0x0`	`FifoLevel` `0x0`

imgcfg_fifo_status Fields

Bit	Name	Description	Access	Reset
9	`FifoEmpty`	Read 1 -> Fifo Empty 0 -> Fifo NOT Empty	`RO`	`0x1`
8	`FifoFull`	Read 1 -> Fifo Full 0 -> Fifo NOT full	`RO`	`0x0`
7:0	`FifoLevel`	Number of words remaining in FPGA Image Configuration Fifo. Maximum value is 0x64	`RO`	`0x0`