jtag_data_w

         A write to this field initiates a write to the TxFifo with the value provided. Please note that this is always a 32bit write, and lower 16 of these bits will be transferred over TDI and upper 16 of these bits will be transferred over TMS once the transfer is initiated. A write to this fifo when full will just be ignored. Also it is allowed to keep writing this fifo without actually intiating a transfer. A typical scenario where this is applicable is if the software want to keep a fixed number of bits ready for JTAG interface before kicking it off.

Both the fifos are 8 words deep. So you can have up to 128 bits buffered in the FIFOs. If you have more than 128 bits to be transferred, and want continuous transfer software should make sure proper data flow to avoid a Tx-Fifo under-run or Rx-Fifo over-run. A Rx-Fifo over-run will cause silent data loss, and a Tx-Fifo under-run will stop the transfer, and will stop the TCK toggles, till another transfer is initiated by software.
At 5MHz jtag clock 16x100/5 = 320 cycles of FPGA manager clock to transfer 1 word of data
At 25Mhz jtag clock 16x100/25 = 64 cycles of FPGA manager clock to transfer 1 word of data.