usb_hostgrp Address Map

Module Instance Base Address End Address
i_usbotg_0_hostgrp 0xFFB00400 0xFFB007FF
i_usbotg_1_hostgrp 0xFFB40400 0xFFB407FF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
hcfg 0x0 32 RW 0x200 
Host Configuration Register
hfir 0x4 32 RW 0xEA60 
Host Frame Interval Register
hfnum 0x8 32 RO 0x3FFF 
Host Frame Number/Frame Time Remaining Register
hptxsts 0x10 32 RO 0x102000 
Host Periodic Transmit FIFO/Queue Status Register
haint 0x14 32 RO 0x0 
Host All Channels Interrupt Register
haintmsk 0x18 32 RW 0x0 
Host All Channels Interrupt Mask Register
hflbaddr 0x1C 32 RW 0x0 
Host Frame List Base Address Register
hprt 0x40 32 RW 0x0 
Host Port Control and Status Register
hcchar0 0x100 32 RW 0x0 
Host Channel 0 Characteristics Register
hcsplt0 0x104 32 RW 0x0 
Host Channel 0 Split Control Register
hcint0 0x108 32 RW 0x0 
Host Channel 0 Interrupt Register
hcintmsk0 0x10C 32 RW 0x0 
Host Channel 0 Interrupt Mask Register
hctsiz0 0x110 32 RW 0x0 
Host Channel 0 Transfer Size Register
hcdma0 0x114 32 RW 0x0 
Host Channel 0 DMA Address Register
hcdmab0 0x11C 32 RW 0x0 
Host Channel 0 DMA Buffer Address Register
hcchar1 0x120 32 RW 0x0 
Host Channel 1 Characteristics Register
hcsplt1 0x124 32 RW 0x0 
Host Channel 1 Split Control Register
hcint1 0x128 32 RW 0x0 
Host Channel 1 Interrupt Register
hcintmsk1 0x12C 32 RW 0x0 
Host Channel 1 Interrupt Mask Register
hctsiz1 0x130 32 RW 0x0 
Host Channel 1 Transfer Size Register
hcdma1 0x134 32 RW 0x0 
Host Channel 1 DMA Address Register
hcdmab1 0x13C 32 RW 0x0 
Host Channel 1 DMA Buffer Address Register
hcchar2 0x140 32 RW 0x0 
Host Channel 2 Characteristics Register
hcsplt2 0x144 32 RW 0x0 
Host Channel 2 Split Control Register
hcint2 0x148 32 RW 0x0 
Host Channel 2 Interrupt Register
hcintmsk2 0x14C 32 RW 0x0 
Host Channel 2 Interrupt Mask Register
hctsiz2 0x150 32 RW 0x0 
Host Channel 2 Transfer Size Register
hcdma2 0x154 32 RW 0x0 
Host Channel 2 DMA Address Register
hcdmab2 0x15C 32 RW 0x0 
Host Channel 2 DMA Buffer Address Register
hcchar3 0x160 32 RW 0x0 
Host Channel 3 Characteristics Register
hcsplt3 0x164 32 RW 0x0 
Host Channel 3 Split Control Register
hcint3 0x168 32 RW 0x0 
Host Channel 3 Interrupt Register
hcintmsk3 0x16C 32 RW 0x0 
Host Channel 3 Interrupt Mask Register
hctsiz3 0x170 32 RW 0x0 
Host Channel 3 Transfer Size Register
hcdma3 0x174 32 RW 0x0 
Host Channel 3 DMA Address Register
hcdmab3 0x17C 32 RW 0x0 
Host Channel 3 DMA Buffer Address Register
hcchar4 0x180 32 RW 0x0 
Host Channel 4 Characteristics Register
hcsplt4 0x184 32 RW 0x0 
Host Channel 4 Split Control Register
hcint4 0x188 32 RW 0x0 
Host Channel 4 Interrupt Register
hcintmsk4 0x18C 32 RW 0x0 
Host Channel 4 Interrupt Mask Register
hctsiz4 0x190 32 RW 0x0 
Host Channel 4 Transfer Size Register
hcdma4 0x194 32 RW 0x0 
Host Channel 4 DMA Address Register
hcdmab4 0x19C 32 RW 0x0 
Host Channel 4 DMA Buffer Address Register
hcchar5 0x1A0 32 RW 0x0 
Host Channel 5 Characteristics Register
hcsplt5 0x1A4 32 RW 0x0 
Host Channel 5 Split Control Register
hcint5 0x1A8 32 RW 0x0 
Host Channel 5 Interrupt Register
hcintmsk5 0x1AC 32 RW 0x0 
Host Channel 5 Interrupt Mask Register
hctsiz5 0x1B0 32 RW 0x0 
Host Channel 5 Transfer Size Register
hcdma5 0x1B4 32 RW 0x0 
Host Channel 5 DMA Address Register
hcdmab5 0x1BC 32 RW 0x0 
Host Channel 5 DMA Buffer Address Register
hcchar6 0x1C0 32 RW 0x0 
Host Channel 6 Characteristics Register
hcsplt6 0x1C4 32 RW 0x0 
Host Channel 6 Split Control Register
hcint6 0x1C8 32 RW 0x0 
Host Channel 6 Interrupt Register
hcintmsk6 0x1CC 32 RW 0x0 
Host Channel 6 Interrupt Mask Register
hctsiz6 0x1D0 32 RW 0x0 
Host Channel 6 Transfer Size Register
hcdma6 0x1D4 32 RW 0x0 
Host Channel 6 DMA Address Register
hcdmab6 0x1DC 32 RW 0x0 
Host Channel 6 DMA Buffer Address Register
hcchar7 0x1E0 32 RW 0x0 
Host Channel 7 Characteristics Register
hcsplt7 0x1E4 32 RW 0x0 
Host Channel 7 Split Control Register
hcint7 0x1E8 32 RW 0x0 
Host Channel 7 Interrupt Register
hcintmsk7 0x1EC 32 RW 0x0 
Host Channel 7 Interrupt Mask Register
hctsiz7 0x1F0 32 RW 0x0 
Host Channel 7 Transfer Size Register
hcdma7 0x1F4 32 RW 0x0 
Host Channel 7 DMA Address Register
hcdmab7 0x1FC 32 RW 0x0 
Host Channel 7 DMA Buffer Address Register
hcchar8 0x200 32 RW 0x0 
Host Channel 8 Characteristics Register
hcsplt8 0x204 32 RW 0x0 
Host Channel 8 Split Control Register
hcint8 0x208 32 RW 0x0 
Host Channel 8 Interrupt Register
hcintmsk8 0x20C 32 RW 0x0 
Host Channel 8 Interrupt Mask Register
hctsiz8 0x210 32 RW 0x0 
Host Channel 8 Transfer Size Register
hcdma8 0x214 32 RW 0x0 
Host Channel 8 DMA Address Register
hcdmab8 0x21C 32 RW 0x0 
Host Channel 8 DMA Buffer Address Register
hcchar9 0x220 32 RW 0x0 
Host Channel 9 Characteristics Register
hcsplt9 0x224 32 RW 0x0 
Host Channel 9 Split Control Register
hcint9 0x228 32 RW 0x0 
Host Channel 9 Interrupt Register
hcintmsk9 0x22C 32 RW 0x0 
Host Channel 9 Interrupt Mask Register
hctsiz9 0x230 32 RW 0x0 
Host Channel 9 Transfer Size Register
hcdma9 0x234 32 RW 0x0 
Host Channel 9 DMA Address Register
hcdmab9 0x23C 32 RW 0x0 
Host Channel 9 DMA Buffer Address Register
hcchar10 0x240 32 RW 0x0 
Host Channel 10 Characteristics Register
hcsplt10 0x244 32 RW 0x0 
Host Channel 10 Split Control Register
hcint10 0x248 32 RW 0x0 
Host Channel 10 Interrupt Register
hcintmsk10 0x24C 32 RW 0x0 
Host Channel 10 Interrupt Mask Register
hctsiz10 0x250 32 RW 0x0 
Host Channel 10 Transfer Size Register
hcdma10 0x254 32 RW 0x0 
Host Channel 10 DMA Address Register
hcdmab10 0x25C 32 RW 0x0 
Host Channel 10 DMA Buffer Address Register
hcchar11 0x260 32 RW 0x0 
Host Channel 11 Characteristics Register
hcsplt11 0x264 32 RW 0x0 
Host Channel 11 Split Control Register
hcint11 0x268 32 RW 0x0 
Host Channel 11 Interrupt Register
hcintmsk11 0x26C 32 RW 0x0 
Host Channel 11 Interrupt Mask Register
hctsiz11 0x270 32 RW 0x0 
Host Channel 11 Transfer Size Register
hcdma11 0x274 32 RW 0x0 
Host Channel 11 DMA Address Register
hcdmab11 0x27C 32 RW 0x0 
Host Channel 11 DMA Buffer Address Register
hcchar12 0x280 32 RW 0x0 
Host Channel 12 Characteristics Register
hcsplt12 0x284 32 RW 0x0 
Host Channel 12 Split Control Register
hcint12 0x288 32 RW 0x0 
Host Channel 12 Interrupt Register
hcintmsk12 0x28C 32 RW 0x0 
Host Channel 12 Interrupt Mask Register
hctsiz12 0x290 32 RW 0x0 
Host Channel 12 Transfer Size Register
hcdma12 0x294 32 RW 0x0 
Host Channel 12 DMA Address Register
hcdmab12 0x29C 32 RW 0x0 
Host Channel 12 DMA Buffer Address Register
hcchar13 0x2A0 32 RW 0x0 
Host Channel 13 Characteristics Register
hcsplt13 0x2A4 32 RW 0x0 
Host Channel 13 Split Control Register
hcint13 0x2A8 32 RW 0x0 
Host Channel 13 Interrupt Register
hcintmsk13 0x2AC 32 RW 0x0 
Host Channel 13 Interrupt Mask Register
hctsiz13 0x2B0 32 RW 0x0 
Host Channel 13 Transfer Size Register
hcdma13 0x2B4 32 RW 0x0 
Host Channel 13 DMA Address Register
hcdmab13 0x2BC 32 RW 0x0 
Host Channel 13 DMA Buffer Address Register
hcchar14 0x2C0 32 RW 0x0 
Host Channel 14 Characteristics Register
hcsplt14 0x2C4 32 RW 0x0 
Host Channel 14 Split Control Register
hcint14 0x2C8 32 RW 0x0 
Host Channel 14 Interrupt Register
hcintmsk14 0x2CC 32 RW 0x0 
Host Channel 14 Interrupt Mask Register
hctsiz14 0x2D0 32 RW 0x0 
Host Channel 14 Transfer Size Register
hcdma14 0x2D4 32 RW 0x0 
Host Channel 14 DMA Address Register
hcdmab14 0x2DC 32 RW 0x0 
Host Channel 14 DMA Buffer Address Register
hcchar15 0x2E0 32 RW 0x0 
Host Channel 15 Characteristics Register
hcsplt15 0x2E4 32 RW 0x0 
Host Channel 15 Split Control Register
hcint15 0x2E8 32 RW 0x0 
Host Channel 15 Interrupt Register
hcintmsk15 0x2EC 32 RW 0x0 
Host Channel 15 Interrupt Mask Register
hctsiz15 0x2F0 32 RW 0x0 
Host Channel 15 Transfer Size Register
hcdma15 0x2F4 32 RW 0x0 
Host Channel 15 DMA Address Register
hcdmab15 0x2FC 32 RW 0x0 
Host Channel 15 DMA Buffer Address Register