hcdma0

         Host Channel 0 DMA Address Register
Module Instance Base Address Register Address
i_usbotg_0_hostgrp 0xFFB00400 0xFFB00514
i_usbotg_1_hostgrp 0xFFB40400 0xFFB40514

Offset: 0x114

Access: RW

Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

hcdma0

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

hcdma0

RW 0x0

hcdma0 Fields

Bit Name Description Access Reset
31:0 hcdma0

Buffer DMA Mode:

[31:0] DMA Address (DMAAddr)

This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.

Scatter-Gather DMA (DescDMA) Mode:
[31:9] (Non Isoc) Non-Isochronous:
[31:N] (Isoc) Isochronous:

This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.

This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as per Table below

[31:N] Base Address
[N-1:3] Offset
[2:0] 000
HS ISOC
nTD N
7 6
15 7
31 8
63 9
127 10
255 11
FS ISOC
nTD N
1 4
3 5
7 6
15 7
31 8
63 9

[N-1:3] (Isoc):

[8:3] (Non Isoc): Current Transfer Desc(CTD):

Non Isochronous:

This value is in terms of number of descriptors. The values can be from 0 to 63.

  • 0 - 1 descriptor.
  • 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the 6th descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.

Isochronous:

CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.Scatter-Gather DMA (DescDMA) Mode:

[31:9] (Non Isoc) Non-Isochronous:

[31:N] (Isoc) Isochronous:

This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.

This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as per Table below
[31:N] Base Address
[N-1:3] Offset
[2:0] 000
HS ISOC
nTD N
7 6
15 7
31 8
63 9
127 10
255 11
FS ISOC
nTD N
1 4
3 5
7 6
15 7
31 8
63 9

[N-1:3] (Isoc):

[8:3] (Non Isoc): Current Transfer Desc(CTD):

Non Isochronous:

This value is in terms of number of descriptors. The values can be from 0 to 63.

  • 0 - 1 descriptor.
  • 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the 6th descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.

Isochronous:

CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.

 RW 0x0