hcchar4

         Host Channel 4 Characteristics Register

Module Instance	Base Address	Register Address
`i_usbotg_0_hostgrp`	`0xFFB00400`	`0xFFB00580`
`i_usbotg_1_hostgrp`	`0xFFB40400`	`0xFFB40580`

Offset: 0x180

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`hcdmab4` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`hcdmab4` `RW 0x0`

hcchar4 Fields

Bit	Name	Description	Access	Reset
31:0	`hcdmab4`	These registers are present only in case of Scatter/Gather DMA. These registers are implemented in RAM instead of flop-based implementation. Holds the current buffer address. This register is updated as and when the data transfer for the corresponding end point is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

hcdmab4

These  registers  are  present  only  in  case  of  Scatter/Gather DMA. These  registers  are  implemented  in RAM instead of flop-based implementation. Holds  the  current  buffer  address. This register is updated as and when  the  data transfer for the corresponding  end  point  is  in progress. This register  is  present  only  in Scatter/Gather DMA mode. Otherwise this field is reserved.

RW

0x0