hfir

         Host Frame Interval Register

Module Instance	Base Address	Register Address
`i_usbotg_0_hostgrp`	`0xFFB00400`	`0xFFB00404`
`i_usbotg_1_hostgrp`	`0xFFB40400`	`0xFFB40404`

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`															`hfirrldctrl` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`frint` `RW 0xEA60`

hfir Fields

Bit

Name

Description

Access

Reset

hfirrldctrl

Reload Control (HFIRRldCtrl)
This bit allows dynamic reloading of the HFIR register during run time. 
1'b0 : The HFIR cannot be reloaded dynamically
1'b1: the HFIR can be dynamically reloaded during runtime. 
This bit needs to be programmed during initial configuration and its value should not be changed during runtime.

Value	Description
0x0	DISABLED
0x1	ENABLED

RW

0x0

15:0

frint

Frame Interval (FrInt)
The value that the application programs to this field specifies
the interval between two consecutive SOFs (FS) or micro-
SOFs (HS) or Keep-Alive tokens (HS). This field contains the
number of PHY clocks that constitute the required frame
interval. The Default value Set in this field For a FS operation
when the PHY clock frequency is 60 MHz. The application can
write a value to this register only after the Port Enable bit of the
Host Port Control and Status register (HPRT.PrtEnaPort) has
been Set. If no value is programmed, the core calculates the
value based on the PHY clock specified in the FS/LS PHY
Clock Select field of the Host Configuration register
(HCFG.FSLSPclkSel). Do not change the value of this field
after the initial configuration.
 125 s * (PHY clock frequency For HS)
 1 ms * (PHY clock frequency For FS/LS)

RW

0xEA60