pinmux Summary

HPS Pinmux CSR.

Base Address: 0x10D13000


Register Address Offset	Bit Fields
`i_dedio_pinmux__pinmux_csr__10d13000__csr__SEG_L4_SHR_IOManager_0x0_0x1000`
`pin0sel` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin1sel` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin2sel` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin3sel` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin4sel` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin5sel` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin6sel` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin7sel` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin8sel` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin9sel` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin10sel` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin11sel` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin12sel` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin13sel` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin14sel` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin15sel` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin16sel` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin17sel` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin18sel` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin19sel` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin20sel` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin21sel` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin22sel` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin23sel` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin24sel` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin25sel` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin26sel` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin27sel` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin28sel` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin29sel` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin30sel` `0x120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin31sel` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin32sel` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin33sel` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin34sel` `0x136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin35sel` `0x140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin36sel` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin37sel` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin38sel` `0x152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin39sel` `0x156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin40sel` `0x256` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin41sel` `0x260` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin42sel` `0x264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin43sel` `0x268` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin44sel` `0x272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin45sel` `0x276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin46sel` `0x280` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`pin47sel` `0x284` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`												`val` `RW 0x8`
`io0ctrl` `0x304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io1ctrl` `0x308` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io2ctrl` `0x312` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io3ctrl` `0x316` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io4ctrl` `0x320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io5ctrl` `0x324` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io6ctrl` `0x328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io7ctrl` `0x332` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io8ctrl` `0x336` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io9ctrl` `0x340` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io10ctrl` `0x344` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io11ctrl` `0x348` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io12ctrl` `0x352` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io13ctrl` `0x356` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io14ctrl` `0x360` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io15ctrl` `0x364` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io16ctrl` `0x368` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io17ctrl` `0x372` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io18ctrl` `0x376` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io19ctrl` `0x380` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io20ctrl` `0x384` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io21ctrl` `0x388` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io22ctrl` `0x392` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io23ctrl` `0x396` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io24ctrl` `0x400` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io25ctrl` `0x404` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io26ctrl` `0x408` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io27ctrl` `0x412` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io28ctrl` `0x512` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io29ctrl` `0x516` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io30ctrl` `0x520` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io31ctrl` `0x524` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io32ctrl` `0x528` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io33ctrl` `0x532` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io34ctrl` `0x536` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io35ctrl` `0x540` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io36ctrl` `0x544` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io37ctrl` `0x548` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io38ctrl` `0x552` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io39ctrl` `0x556` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io40ctrl` `0x560` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io41ctrl` `0x564` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io42ctrl` `0x568` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io43ctrl` `0x572` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io44ctrl` `0x576` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io45ctrl` `0x580` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io46ctrl` `0x584` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`io47ctrl` `0x588` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`						`iodt_config` `RW 0x0`	`iodt_en` `RW 0x0`	`iwkpullctrl` `RW 0x1`			`ihysen` `RW 0x1`	`ioden` `RW 0x0`	`islewctrl` `RW 0x1`	`idrvctrl` `RW 0x0`
`pinmux_emac0_usefpga` `0x768` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_emac1_usefpga` `0x772` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_emac2_usefpga` `0x776` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_i2c0_usefpga` `0x780` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_i2c1_usefpga` `0x784` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_i2c_emac0_usefpga` `0x788` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_i2c_emac1_usefpga` `0x792` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_i2c_emac2_usefpga` `0x796` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_spim0_usefpga` `0x808` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_spim1_usefpga` `0x812` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_spis0_usefpga` `0x816` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_spis1_usefpga` `0x820` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_uart0_usefpga` `0x824` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_uart1_usefpga` `0x828` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_mdio0_usefpga` `0x832` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_mdio1_usefpga` `0x836` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_mdio2_usefpga` `0x840` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_jtag_usefpga` `0x848` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`io0_delay` `0x1024` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io1_delay` `0x1028` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io2_delay` `0x1032` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io3_delay` `0x1036` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io4_delay` `0x1040` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io5_delay` `0x1044` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io6_delay` `0x1048` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io7_delay` `0x1052` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io8_delay` `0x1056` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io9_delay` `0x1060` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io10_delay` `0x1064` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io11_delay` `0x1068` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io12_delay` `0x1072` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io13_delay` `0x1076` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io14_delay` `0x1080` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io15_delay` `0x1084` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io16_delay` `0x1088` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io17_delay` `0x1092` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io18_delay` `0x1096` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io19_delay` `0x1100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io20_delay` `0x1104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io21_delay` `0x1108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io22_delay` `0x1112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io23_delay` `0x1116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io24_delay` `0x1120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io25_delay` `0x1124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io26_delay` `0x1128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io27_delay` `0x1132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io28_delay` `0x1136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io29_delay` `0x1140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io30_delay` `0x1144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io31_delay` `0x1148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io32_delay` `0x1152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io33_delay` `0x1156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io34_delay` `0x1160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io35_delay` `0x1164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io36_delay` `0x1168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io37_delay` `0x1172` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io38_delay` `0x1176` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io39_delay` `0x1180` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io40_delay` `0x1184` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io41_delay` `0x1188` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io42_delay` `0x1192` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io43_delay` `0x1196` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io44_delay` `0x1200` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io45_delay` `0x1204` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io46_delay` `0x1208` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`io47_delay` `0x1212` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`	`output_val_en` `RW 0x0`		`output_val` `RW 0x0`					`Reserved_2` `RO 0x0`	`input_val_en` `RW 0x0`		`input_val` `RW 0x0`
`pinmux_i3c0_usefpga` `0x1216` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`
`pinmux_i3c1_usefpga` `0x1220` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`sel` `RW 0x0`