pinmux_uart0_usefpga

         Selection between HPS Pin and FPGA Interface for UART0 signals.  NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.


Module Instance	Base Address	Register Address
`i_dedio_pinmux__pinmux_csr__10d13000__csr__SEG_L4_SHR_IOManager_0x0_0x1000`	`0x10D13000`	`0x10D13338`

Size: 32

Offset: 0x338

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`															`sel` `RW 0x0`

pinmux_uart0_usefpga Fields

Bit Name Description Access Reset

31:1

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

sel

Select connection for UART0.

Value	Description
0	UART0 uses HPS IO Pins.
1	UART0 uses the FPGA Inteface.

RW

0x0