pin29sel
HPS Pinmux Select for IO5
| Module Instance | Base Address | Register Address |
|---|---|---|
i_dedio_pinmux__pinmux_csr__10d13000__csr__SEG_L4_SHR_IOManager_0x0_0x1000
|
0x10D13000
|
0x10D13074
|
Size: 32
Offset: 0x74
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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pin29sel Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:4 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
| 3:0 |
val
|
Select value determines which interface has been selected for IO5. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9. 0000 (0) -- Pin connected to emac1.txd1 0001 (1) -- Pin connected to i3c1.scl 0010 (2) -- Pin connected to trace.d5 0011 (3) -- Pin connected to nand.ADQ2 / sdmmc.data2 0100 (4) -- Pin connected to emac2.ppstrig2 0101 (5) -- Pin connected to uart1.rts_n 0110 (6) -- Pin connected to spis1.mosi 0111 (7) -- NA 1000 (8) -- Pin connected to gpio1.io5 1001 (9) -- Pin connected to cm.hps_osc_clk |
RW
|
0x8
|