io9_delay 

         Adds the delay chains in IO9.
Module Instance Base Address Register Address
i_dedio_pinmux__pinmux_csr__10d13000__csr__SEG_L4_SHR_IOManager_0x0_0x1000 0x10D13000 0x10D13424

Size: 32

Offset: 0x424

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_4

RO 0x0

output_val_en

RW 0x0

output_val

RW 0x0

Reserved_2

RO 0x0

input_val_en

RW 0x0

input_val

RW 0x0

io9_delay Fields

Bit Name Description Access Reset
31:15 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
14:13 output_val_en 
These bits are used to enable the delay chains on the output path.   
00 - Bypasses the delay chain ; 
01 - Selects delay from 0 to 15 chain delay as programmed by the output_val field. ; 
10 - NA ; 
11 - Selects delay from 16 to 30 delay chains as programmed by output_val field.
Value Description
0 Bypasses the delay chains
1 Selects the delay chain ranging from 0 to 15 (Intrinsic IO delay + 1Minimum + xChain delay)
3 Selects the delay chain ranging from 16 to 30 ((Intrinsic IO delay + 2Minimum + xChain delay)
RW 0x0
12:8 output_val 
Depending on the value, it adds the chain delays in the output path of the Pinmux.
Value Description
0 Intrinsic IO delay + Minimum Chain delay . Selects the data through the delay chain but no delay cell is enabled.
1 Intrinsic IO delay + Minimum+1Chain delay
2 Intrinsic IO delay + Minimum +2Chain delay
3 Intrinsic IO delay + Minimum +3Chain delay
4 Intrinsic IO delay + Minimum +4Chain delay
5 Intrinsic IO delay + Minimum+5 Chain delay
6 Intrinsic IO delay + Minimum +6Chain delay
7 Intrinsic IO delay + Minimum +7Chain delay
8 Intrinsic IO delay + Minimum +8Chain delay
9 Intrinsic IO delay + Minimum+9 Chain delay
10 Intrinsic IO delay + Minimum +10Chain delay
11 Intrinsic IO delay + Minimum+11 Chain delay
12 Intrinsic IO delay + Minimum +12Chain delay
13 Intrinsic IO delay + Minimum+13 Chain delay
14 Intrinsic IO delay + Minimum +14Chain delay
15 Intrinsic IO delay + Minimum +15Chain delay
16 Intrinsic IO delay + Minimum +16Chain delay
17 Intrinsic IO delay + Minimum +17Chain delay
18 Intrinsic IO delay + Minimum +18Chain delay
19 Intrinsic IO delay + Minimum +19Chain delay
20 Intrinsic IO delay + Minimum +20Chain delay
21 Intrinsic IO delay + Minimum +21Chain delay
22 Intrinsic IO delay + Minimum +22Chain delay
23 Intrinsic IO delay + Minimum +23Chain delay
24 Intrinsic IO delay + Minimum +24Chain delay
25 Intrinsic IO delay + Minimum +25Chain delay
26 Intrinsic IO delay + Minimum +26Chain delay
27 Intrinsic IO delay + Minimum +27Chain delay
28 Intrinsic IO delay + Minimum +28Chain delay
29 Intrinsic IO delay + Minimum +29Chain delay
30 Intrinsic IO delay + Minimum +30Chain delay
RW 0x0
7 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
6:5 input_val_en 
These bits are used to enable the delay chains in the input path.  
 00 - Bypasses the delay chain ; 
 01 - Selects delay from 0 to 15 chain delay as programmed by the input_val field. ; 
 10 - NA ; 
 11 - Selects delay from 16 to 30 delay chains as programmed by input_val field.
Value Description
0 Bypasses the delay chains
1 Selects the delay chain ranging from 0 to 15 (Intrinsic IO delay + 1Minimum + xChain delay)
3 Selects the delay chain ranging from 16 to 30 ((Intrinsic IO delay + 2Minimum + xChain delay)
RW 0x0
4:0 input_val 
Depending on the value, it adds the chain delays in the input path of the Pinmux.
Value Description
0 Intrinsic IO delay + Minimum Chain delay . Selects the data through the delay chain but no delay cell is enabled.
1 Intrinsic IO delay + Minimum+1Chain delay
2 Intrinsic IO delay + Minimum +2Chain delay
3 Intrinsic IO delay + Minimum +3Chain delay
4 Intrinsic IO delay + Minimum +4Chain delay
5 Intrinsic IO delay + Minimum+5 Chain delay
6 Intrinsic IO delay + Minimum +6Chain delay
7 Intrinsic IO delay + Minimum +7Chain delay
8 Intrinsic IO delay + Minimum +8Chain delay
9 Intrinsic IO delay + Minimum+9 Chain delay
10 Intrinsic IO delay + Minimum +10Chain delay
11 Intrinsic IO delay + Minimum+11 Chain delay
12 Intrinsic IO delay + Minimum +12Chain delay
13 Intrinsic IO delay + Minimum+13 Chain delay
14 Intrinsic IO delay + Minimum +14Chain delay
15 Intrinsic IO delay + Minimum +15Chain delay
16 Intrinsic IO delay + Minimum +16Chain delay
17 Intrinsic IO delay + Minimum +17Chain delay
18 Intrinsic IO delay + Minimum +18Chain delay
19 Intrinsic IO delay + Minimum +19Chain delay
20 Intrinsic IO delay + Minimum +20Chain delay
21 Intrinsic IO delay + Minimum +21Chain delay
22 Intrinsic IO delay + Minimum +22Chain delay
23 Intrinsic IO delay + Minimum +23Chain delay
24 Intrinsic IO delay + Minimum +24Chain delay
25 Intrinsic IO delay + Minimum +25Chain delay
26 Intrinsic IO delay + Minimum +26Chain delay
27 Intrinsic IO delay + Minimum +27Chain delay
28 Intrinsic IO delay + Minimum +28Chain delay
29 Intrinsic IO delay + Minimum +29Chain delay
30 Intrinsic IO delay + Minimum +30Chain delay
RW 0x0