clkmgr Summary

Registers in the Clock Manager module

Base Address: 0x10D10000


Register Address Offset	Bit Fields
`i_clk_mgr__clkmgr_csr__10d10000__clkmgr__SEG_L4_SHR_ClockManager_0x0_0x1000`
`ctrl` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`swctrlbtclksel` `RW 0x0`	`swctrlbtclken` `RW 0x0`	`Reserved_1` `RO 0x1`							`bootmode` `RW 0x1`
`stat` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`						`bootclksrc` `RO 0x0`	`bootmode` `RO 0x0`	`Reserved_5` `RO 0x7`						`perf_trans` `RO 0x0`	`perplllocked` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x7`						`main_trans` `RO 0x0`	`mainplllocked` `RO 0x0`	`Reserved_1` `RO 0x0`							`busy` `RO 0x0`
`testioctrl` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x8`															`debugclksel` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x2`						`periclksel` `RW 0x0`		`Reserved_1` `RO 0x2`						`mainclksel` `RW 0x0`
`intrgen` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`en` `RW 0x0`
`intrmsk` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`												`perlocklost` `RW 0x0`	`mainlocklost` `RW 0x0`	`perlockachieved` `RW 0x0`	`mainlockachieved` `RW 0x0`
`intrclr` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `WO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `WO 0x0`												`perlocklost` `RW 0x0`	`mainlocklost` `RW 0x0`	`perlockachieved` `RW 0x0`	`mainlockachieved` `RW 0x0`
`intrsts` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`												`perlocklost` `RO 0x0`	`mainlocklost` `RO 0x0`	`perlockachieved` `RO 0x0`	`mainlockachieved` `RO 0x0`
`intrstk` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`												`perlocklost` `RO 0x0`	`mainlocklost` `RO 0x0`	`perlockachieved` `RO 0x0`	`mainlockachieved` `RO 0x0`
`intrraw` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`												`perlocklost` `RO 0x0`	`mainlocklost` `RO 0x0`	`perlockachieved` `RO 0x0`	`mainlockachieved` `RO 0x0`