intrraw

         Realtime Status of the bits which could have caused interrupt.

Set and clear by hardware.
Realtime behavior. Bits follow the current hardware status.


Module Instance	Base Address	Register Address
`i_clk_mgr__clkmgr_csr__10d10000__clkmgr__SEG_L4_SHR_ClockManager_0x0_0x1000`	`0x10D10000`	`0x10D10020`

Size: 32

Offset: 0x20

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_4` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_4` `RO 0x0`												`perlocklost` `RO 0x0`	`mainlocklost` `RO 0x0`	`perlockachieved` `RO 0x0`	`mainlockachieved` `RO 0x0`

intrraw Fields


Bit	Name	Description	Access	Reset
31:4	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
3	`perlocklost`	Raw signal (before masking) for periph PLL lock lost. It comed from clock manager	`RO`	`0x0`
2	`mainlocklost`	Raw signal (before masking) for main PLL lock lost. It comed from clock manager	`RO`	`0x0`
1	`perlockachieved`	Raw signal (before masking) for periph PLL lock achieved. It comed from clock manager	`RO`	`0x0`
0	`mainlockachieved`	Raw signal (before masking) for main PLL lock achieved. It comed from clock manager	`RO`	`0x0`