intrclr 

         Interrupt Clear.

Writing 1 to a particular bit will cause that interrupt to be cleared if it was set.
Module Instance Base Address Register Address
i_clk_mgr__clkmgr_csr__10d10000__clkmgr__SEG_L4_SHR_ClockManager_0x0_0x1000 0x10D10000 0x10D10014

Size: 32

Offset: 0x14

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_4

WO 0x0

perlocklost

RW 0x0

mainlocklost

RW 0x0

perlockachieved

RW 0x0

mainlockachieved

RW 0x0

intrclr Fields

Bit Name Description Access Reset
31:4 Reserved_4 
Reserved bitfield added by Magillem
 WO 0x0
3 perlocklost 
This is used to clear sticky periph PLL lock lost signal.
 RW 0x0
2 mainlocklost 
This is used to clear sticky main PLL lock lost signal.
 RW 0x0
1 perlockachieved 
This is used to clear sticky periph PLL lock achieved signal.
 RW 0x0
0 mainlockachieved 
This is used to clear sticky main PLL lock achieved signal.
 RW 0x0